Abstract: A semiconductor device can reduce power consumption in a low power mode and includes a first input/output circuit configured to detect a first entry signal transiting at a first time and output a detection signal indicating an entry into a power saving mode according to a result of the detection. A second input/output circuit is configured to receive a second entry signal transiting at a second time earlier than the first time, and a control circuit is configured to block power supplied to the second input/output circuit in response to the detection signal indicating the entry.

Abstract: Provided is an interface circuit for transmitting and receiving data according to a communication protocol. The interface circuit includes: an encoder configured to encode input data to generate transmission data; a transmitter configured to output the transmission data; a data sequence detector configured to detect whether the number of successively same logic values in a data string of the transmission data is equal to or greater than a reference succession number; and a recovery section configured to control a recovery operation with respect to the transmission data, based on a detection result of the data sequence detector. With the interface circuit, data loss is prevented and data reliability is guaranteed.

Abstract: There is provided a digitally controlled oscillator, which is capable of widening its operation range with maintaining its resolution and the maximum frequency at which it operates. The digitally controlled oscillator includes a phase compensation block, a coarse block, and a fine block. The phase compensation block 510 generating a PLL signal PLLCLK and a first clock signal CLK1 which has the same phase and frequency as the PLL signal, in response to a phase control signal DISABLE and a fourth clock signal CLK4. The coarse block 520 generating a second clock signal CLK2 and a third clock signal CLK3 which results from delaying the PLL signal PLLCLK and the first clock signal CLK1 for a given time, in response to a m(integer)-bit coarse A control signal COAR_A and an (m?1)-bit coarse B control signal COAR_B.

Abstract: There is provided a digitally controlled oscillator, which is capable of widening its operation range with maintaining its resolution and the maximum frequency at which it operates. The digitally controlled oscillator includes a phase compensation block, a coarse block, and a fine block. The phase compensation block 510 generating a PLL signal PLLCLK and a first clock signal CLK1 which has the same phase and frequency as the PLL signal, in response to a phase control signal DISABLE and a fourth clock signal CLK4. The coarse block 520 generating a second clock signal CLK2 and a third clock signal CLK3 which results from delaying the PLL signal PLLCLK and the first clock signal CLK1 for a given time, in response to a m(integer)-bit coarse A control signal COAR_A and an (m?1)-bit coarse B control signal COAR_B.