Patents by Inventor Kwang Ho Baek
Kwang Ho Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11636898Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.Type: GrantFiled: June 3, 2021Date of Patent: April 25, 2023Assignee: SK hynix Inc.Inventors: Jung Mi Ko, Kwang Ho Baek, Seong Je Park, Young Don Jung, Ji Hwan Kim, Jung Hwan Lee
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Publication number: 20210287749Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.Type: ApplicationFiled: June 3, 2021Publication date: September 16, 2021Inventors: Jung Mi KO, Kwang Ho BAEK, Seong Je PARK, Young Don JUNG, Ji Hwan KIM, Jung Hwan LEE
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Publication number: 20210280254Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.Type: ApplicationFiled: May 12, 2021Publication date: September 9, 2021Inventors: Jung Mi KO, Kwang Ho BAEK, Seong Je PARK, Young Don JUNG, Ji Hwan KIM, Jung Hwan LEE
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Patent number: 11107541Abstract: The present technology relates to a memory device and method of operating the memory device. The memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit performs a plurality of program loops each including a program operation and a verify operation on selected memory cells of the plurality of memory cells. The control logic controls the peripheral circuit to increase a potential of selected bit lines.Type: GrantFiled: May 13, 2020Date of Patent: August 31, 2021Assignee: SK hynix Inc.Inventors: Young Don Jung, Jung Mi Ko, Kwang Ho Baek, Chang Han Son, Jung Hwan Lee
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Patent number: 11037629Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.Type: GrantFiled: December 27, 2019Date of Patent: June 15, 2021Assignee: SK hynix Inc.Inventors: Jung Mi Ko, Kwang Ho Baek, Seong Je Park, Young Don Jung, Ji Hwan Kim, Jung Hwan Lee
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Publication number: 20210166771Abstract: The present technology relates to a memory device and method of operating the memory device. The memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit performs a plurality of program loops each including a program operation and a verify operation on selected memory cells of the plurality of memory cells. The control logic controls the peripheral circuit to increase a potential of selected bit lines.Type: ApplicationFiled: May 13, 2020Publication date: June 3, 2021Applicant: SK hynix Inc.Inventors: Young Don JUNG, Jung Mi KO, Kwang Ho BAEK, Chang Han SON, Jung Hwan LEE
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Patent number: 10998053Abstract: A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.Type: GrantFiled: November 6, 2019Date of Patent: May 4, 2021Assignee: SK hynix Inc.Inventors: Jung Hwan Lee, Jung Mi Ko, Ji Hwan Kim, Kwang Ho Baek, Young Don Jung
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Patent number: 10971234Abstract: Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.Type: GrantFiled: October 31, 2019Date of Patent: April 6, 2021Assignee: SK hynix Inc.Inventors: Jung Hwan Lee, Jung Mi Ko, Ji Hwan Kim, Kwang Ho Baek, Young Don Jung
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Patent number: 10937513Abstract: A semiconductor memory device operates by applying a program pulse to a selected word line, updating a program pulse count value, determining a current sensing mode based upon the program pulse count value, and performing a program verify operation based upon the current sensing mode. The current sensing mode is determined by determining one of an individual state current sensing operation for determining verify pass or fail for one target program state and an all-state current sensing operation for determining verify pass or fail for all target program states.Type: GrantFiled: October 29, 2019Date of Patent: March 2, 2021Assignee: SK hynix Inc.Inventors: Jung Mi Ko, Kwang Ho Baek, Ji Hwan Kim, Seong Je Park, Sung Hoon Ahn, Young Don Jung
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Publication number: 20200381055Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.Type: ApplicationFiled: December 27, 2019Publication date: December 3, 2020Inventors: Jung Mi KO, Kwang Ho BAEK, Seong Je PARK, Young Don JUNG, Ji Hwan KIM, Jung Hwan LEE
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Patent number: 10818360Abstract: The present disclosure relates to a memory device and a memory system including the same. The memory device includes a memory cell storing data, a voltage generation circuit selectively outputting a program voltage and verify voltages in response to an operation control signal, a page buffer including first latches and second latches, and storing first data sensed by a first sensing current in the first latches and second data sensed by a sensing current greater than the first sensing current in the second latches during a verify operation using the verify voltages, and a pass/fail check circuit determining a pass or fail of the verify operation of the memory cell according to the first data and allowable bits.Type: GrantFiled: June 19, 2019Date of Patent: October 27, 2020Assignee: SK hynix Inc.Inventors: Jong Hoon Lee, Ji Hwan Kim, Kwang Ho Baek, Jin Haeng Lee
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Publication number: 20200321042Abstract: A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.Type: ApplicationFiled: November 6, 2019Publication date: October 8, 2020Applicant: SK hynix Inc.Inventors: Jung Hwan LEE, Jung Mi KO, Ji Hwan KIM, Kwang Ho BAEK, Young Don JUNG
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Publication number: 20200321058Abstract: Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.Type: ApplicationFiled: October 31, 2019Publication date: October 8, 2020Applicant: SK hynix Inc.Inventors: Jung Hwan LEE, Jung Mi KO, Ji Hwan KIM, Kwang Ho BAEK, Young Don JUNG
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Publication number: 20200202963Abstract: A semiconductor memory device operates by applying a program pulse to a selected word line, updating a program pulse count value, determining a current sensing mode based upon the program pulse count value, and performing a program verify operation based upon the current sensing mode. The current sensing mode is determined by determining one of an individual state current sensing operation for determining verify pass or fail for one target program state and an all-state current sensing operation for determining verify pass or fail for all target program states.Type: ApplicationFiled: October 29, 2019Publication date: June 25, 2020Applicant: SK hynix Inc.Inventors: Jung Mi KO, Kwang Ho BAEK, Ji Hwan KIM, Seong Je PARK, Sung Hoon AHN, Young Don JUNG
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Publication number: 20200143886Abstract: The present disclosure relates to a memory device and a memory system including the same. The memory device includes a memory cell storing data, a voltage generation circuit selectively outputting a program voltage and verify voltages in response to an operation control signal, a page buffer including first latches and second latches, and storing first data sensed by a first sensing current in the first latches and second data sensed by a sensing current greater than the first sensing current in the second latches during a verify operation using the verify voltages, and a pass/fail check circuit determining a pass or fail of the verify operation of the memory cell according to the first data and allowable bits.Type: ApplicationFiled: June 19, 2019Publication date: May 7, 2020Applicant: SK hynix Inc.Inventors: Jong Hoon LEE, Ji Hwan KIM, Kwang Ho BAEK, Jin Haeng LEE
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Patent number: 10636492Abstract: A method of operating a memory device having improved threshold voltage distributions of select transistors, the memory device including a plurality of cell strings each including a plurality of source select transistors, a plurality of memory cells, and a plurality of drain select transistors stacked in a vertical direction to a substrate include performing a first program operation to program at least one source select transistor coupled to a first source select line adjacent to a common source line, among the plurality of source select transistors, using a fixed program voltage, and performing a second program operation to program at least one source select transistor coupled to a second source select line adjacent to the first source select line, among the plurality of source select transistors, using an incremental step pulse program (ISPP) method after the first program operation is completed.Type: GrantFiled: July 31, 2018Date of Patent: April 28, 2020Assignee: SK hynix Inc.Inventors: Kwang Ho Baek, Jong Hoon Lee
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Publication number: 20190189216Abstract: A method of operating a memory device having improved threshold voltage distributions of select transistors, the memory device including a plurality of cell strings each including a plurality of source select transistors, a plurality of memory cells, and a plurality of drain select transistors stacked in a vertical direction to a substrate include performing a first program operation to program at least one source select transistor coupled to a first source select line adjacent to a common source line, among the plurality of source select transistors, using a fixed program voltage, and performing a second program operation to program at least one source select transistor coupled to a second source select line adjacent to the first source select line, among the plurality of source select transistors, sing an incremental step pulse program (ISPP) method after the first program operation is completed.Type: ApplicationFiled: July 31, 2018Publication date: June 20, 2019Inventors: Kwang Ho BAEK, Jong Hoon LEE
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Patent number: 9123396Abstract: A semiconductor device may include first conductive patterns coupled to a common source and selection lines of a memory block formed at a substrate, second conductive patterns configured to form a bit line coupled to the memory block, and third conductive patterns configured to transmit a block selection signal to couple local lines of the memory block to global lines. The first to third conductive patterns are arranged in different layers over the memory block.Type: GrantFiled: August 6, 2013Date of Patent: September 1, 2015Assignee: SK HYNIX INC.Inventors: Chang Man Son, Chang Hyuk Lee, Go Hyun Lee, Kwang Ho Baek
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Patent number: 9001589Abstract: A method of erasing charge trap devices includes applying a first erase voltage to the charge trap devices; applying an erase verify voltage to the charge trap devices; performing a current first fail bit check operation including comparing a first number of charge trap devices, which are determined to be an erase fail based on the erase verify voltage, to a first reference value and determining a pass or fail based on the comparison result; when the current first fail bit check operation is determined to be a fail, determining whether a previous first fail bit check operation performed during a previous erase loop was passed or not; and when the previous first fail bit check operation performed during the previous erase loop was passed, setting a third erase voltage to a same level as a second erase voltage used during the previous erase loop.Type: GrantFiled: February 26, 2013Date of Patent: April 7, 2015Assignee: SK Hynix Inc.Inventor: Kwang Ho Baek
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Patent number: 8923055Abstract: A semiconductor device includes cell strings that each include a plurality of memory cells, a page buffer having latches coupled to bit lines and precharge the bit lines in response to page buffer control signals, a page buffer control circuit configured to generate the page buffer control signals using a high voltage source, and a controller configured to generate control signals for controlling the page buffer control circuit.Type: GrantFiled: June 8, 2012Date of Patent: December 30, 2014Assignee: SK Hynix Inc.Inventors: Kwang Ho Baek, Jin Su Park, Chang Won Yang