Abstract: Silicon carbide power semiconductor device having uniform channel length and manufacturing method thereof disclosed. The power semiconductor device includes a drift region of a first conductivity type, a plurality of body regions of a second conductivity type, being formed to be spaced apart from each other with a preset WS in a horizontal direction in an upper region of the drift region, a JFET region of the first conductivity type and a low-resistance region of the first conductivity type, being formed in a separation space between adjacent body regions to contact their side surfaces with the adjacent body regions and a source region of the first conductivity type, being formed in a surface region in the body region in contact with the low-resistance region to be spaced apart from the low-resistance region by a preset channel length.

Abstract: The present invention relates to an image encoding and decoding technique, and more particularly, to an image encoder and decoder using unidirectional prediction. The image encoder includes a dividing unit to divide a macro block into a plurality of sub-blocks, a unidirectional application determining unit to determine whether an identical prediction mode is applied to each of the plurality of sub-blocks, and a prediction mode determining unit to determine a prediction mode with respect to each of the plurality of sub-blocks based on a determined result of the unidirectional application determining unit.

Abstract: The present invention is a composition for liquid crystal polymer synthesis comprising an alicyclic dicarboxylic acid or its derivative (e.g., 1,4-cyclohexanedicarboxylic acid (CHDA)); an aromatic diol (e.g., hydroquinone (HQ)); an aromatic monocarboxylic acid having 7 to 10 carbon atoms and containing a hydroxyl group (e.g., 4-hydroxybenzoic acid, (HBA)); and an aromatic monocarboxylic acid having 11 to 20 carbon atoms and containing a hydroxyl group (e.g., 6-hydroxy-2-naphthalenecarboxylic acid (HNA)), and a liquid crystal polymer for electrical/electronic products, a polymer resin composition, and a molded product using the same.

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Abstract: Power semiconductor device with dual shield structure in silicon carbide and manufacturing method thereof disclosed.

Abstract: Power semiconductor device with reduced loss and manufacturing method the same disclosed. Power semiconductor device include a first drift region of a first conductivity type, a second drift region of the first conductivity type formed by epitaxially growing on the first drift region and a plurality of buried ion regions of a second conductivity type formed to be buried in the second drift region.

Abstract: Power semiconductor device capable of controlling slope of current and voltage during dynamic switching disclosed. The power semiconductor device may include a semiconductor substrate and a cell array being consisted of a plurality of transistor cells on an active area, wherein each of the plurality of transistor cells may include an emitter region, a body region, a contact region and a gate region, wherein non-uniform threshold voltages may be respectively set in the plurality of transistor cells constituting the cell array, wherein a gate signal may be applied to each of the plurality of transistor cells through an input/output unit, wherein the input/output unit may include a first gate signal path configured for supplying a gate charging current to the gate regions in each of the plurality of transistor cells and a second gate signal path configured for discharging a gate discharging current from the gate region.

Abstract: A hybrid comparator includes an analog signal combiner and a dynamic latch. The analog signal combiner is configured to receive an input analog signal and an input reference signal, and generate an analog output signal by combining the input analog signal and the input reference signal. The dynamic latch is configured to receive the analog output signal and a clock signal, and generate a digital output signal.

Abstract: A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent.

Abstract: A charge-balance power device and a method of manufacturing the charge-balance power device are provided. The charge-balance power device includes: a charge-balance body region in which one or more first conductive type pillars as a first conductive type impurity region and one or more second conductive type pillars as a second conductive type impurity region are arranged; a first conductive type epitaxial layer that is formed on the charge-balance body region; and a transistor region that is formed in the first conductive type epitaxial layer. With this invention, it is possible to form the same charge-balance body region regardless of the structure of the transistor region formed on the top side of wafer.

Abstract: A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent.

Abstract: A MOS-gate power semiconductor device is provided which includes: one or more P-type wells formed under one or more of a gate metal electrode and a gate bus line and electrically connected to an emitter metal electrode; and one or more N-type wells formed in the P-type well and electrically connected to one or more of the gate metal electrode and the gate bus line. According to this configuration, it is possible to suppress deterioration and/or destruction of a device due to an overcurrent.

Abstract: Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type.

Abstract: Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type.

Abstract: An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid unit surrounding a rectangular semiconductor island (102). Each island contains three parallel regions of the opposite conductivity type: the center region (104) is operable as the transistor drain and the two other regions (103 and 105), abutting the isolations, are operable as transistor sources. Transistor gates (106 and 107) are between the parallel regions, completing the formation of two transistors having one common drain. Electrical contacts (108) are placed on both source regions and the drain region. The source contacts are placed so that the spacing (120) between each contact and its respective isolation is at least twice as large as the spacing (121) between each contact and the gate.

Abstract: An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid unit surrounding a rectangular semiconductor island (102). Each island contains three parallel regions of the opposite conductivity type: the center region (104) is operable as the transistor drain and the two other regions (103 and 105), abutting the isolations, are operable as transistor sources. Transistor gates (106 and 107) are between the parallel regions, completing the formation of two transistors having one common drain. Electrical contacts (108) are placed on both source regions and the drain region. The source contacts are placed so that the spacing (120) between each contact and its respective isolation is at least twice as large as the spacing (121) between each contact and the gate.

Abstract: An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid unit surrounding a rectangular substrate island (102). Each island contains two parallel regions of the opposite conductivity type: one region (174) is operable as the transistor drain and the other region (173) is operable as the transistor drain, each region abutting the isolation. A transistor gate (105) is between the parallel regions, completing the formation of a transistor. Electrical contacts (106) are placed on the source region (173) so that the spacing (120) between each contact and the adjacent isolation is at least twice as large as the spacing (121) between each contact and the gate. A plurality of these islands are interconnected to form a multi-finger MOS transistor.

Abstract: An insulated gate bipolar transistor according to the present invention has a first and a second emitter regions. A diffusion region of the first conductive type is formed in the first emitter region of the second conductive type. The second emitter region has a region having a high concentration compared with the remaining portion of the second emitter region. The high concentration region is adjacent to the diffusion region and positioned towards the center of a first conductive type well. In addition, the junction depth of the high concentration region is similar to the diffusion region.

Abstract: An emitter switched thyristor has an enlarged safe operating range. A semiconductor substrate of a first conductivity type (a p-type) is provided and a semiconductor region of a second conductivity type (an n-type) is formed on the substrate. A well region of the first conductivity type is formed within the semiconductor region, and a plurality of well subregions of the second conductivity type are formed within the well region. The well subregions are all separated from each other by a separating portion of the well region. A plurality of electrode contacts are provided, including a gate electrode in contact with the well region and at least first and second cathode electrodes. The second cathode electrode is in contact with the separating portion of the well region.

Abstract: The present invention relates to a method of manufacturing an insulated-gate transistor including a very thin P.sup.- layer as a channel under a gate terminal. The device and method differs from conventional devices and techniques in that the P.sup.- regions are formed by double diffusion. Secondly, the present invention includes channel regions by forming the N.sup.+ regions in the middle of the shallow P.sup.- layer causing the resistance of the JFET regions to be reduced. High-speed operation of the device can be obtained by reducing the input and reverse capacitances which thereby reduces the time delay when power is supplied. The forward voltage drop is reduced by reducing the resistance of the first conductive semiconductor region which is determined by the distance between the second conductive type semiconductor region in its forward turn-on state.