Patents by Inventor KWANG-HUN LEE

KWANG-HUN LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12221820
    Abstract: An embodiment vehicle hinge driving apparatus for driving a vehicle hinge mounted between a door component and a vehicle body includes an actuator, a housing connected to the actuator, an output shaft having an axis aligned with an axis of the housing, and a transmission mechanism configured to vary a torque generated by the actuator and to transmit the torque to the output shaft.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: February 11, 2025
    Assignees: Hyundai Motor Company, Kia Corporation, PHA Co., Ltd., Keyang Electric Machinery Co., Ltd.
    Inventors: Duck Young Kim, Jae Man Cho, Byung Ju Kang, Seung Yup Lee, Kwang Hun Hong
  • Publication number: 20250034075
    Abstract: A method for preparing a recycled raw material uses a waste copolyester. The method for preparing a recycled raw material includes (1) depolymerizing a waste copolyester to obtain a first reactant; (2) removing impurities present in the first reactant to obtain a second reactant; (3) distilling the second reactant to obtain a third reactant containing crude recycled bis-2-hydroxyethyl terephthalate and a fourth reactant containing a recycled diol-ester; and (4) mixing the third reactant with an aqueous solvent and recrystallizing it to obtain a fifth reactant containing recycled bis-2-hydroxyethyl terephthalate and a filtrate.
    Type: Application
    Filed: December 7, 2023
    Publication date: January 30, 2025
    Applicant: SK CHEMICALS CO., LTD.
    Inventors: Ji-Hun KIM, Kwang-Woo PARK, Joong Ki LEE
  • Publication number: 20240330197
    Abstract: A storage device may generate a compression journal based on N target journals among a plurality of journals and store the compression journal in a memory in which the plurality of journals are stored. In this case, each of the plurality of journals may include a logical address area index, an old physical address area index, and a new physical address area index. The new physical address area indexes of target journals may be the same. In addition, the compression journal may include a new physical address area index common to the target journals.
    Type: Application
    Filed: July 19, 2023
    Publication date: October 3, 2024
    Inventors: Kwang Hun LEE, In Sung SONG, Chul Woo LEE, Jin Won JANG, Jae Hoon HEO
  • Publication number: 20240201865
    Abstract: A memory system includes a memory device including a plurality of planes each including a plurality of memory blocks; and a memory controller for controlling the memory device to perform an operation on target blocks among the plurality of memory blocks, to store, in a replacement block, data stored in a bad block, on which the operation fails among the target blocks, and control the memory device to temporarily store, in a backup block, data stored in the other blocks except the bad block among the target blocks according to a number of free blocks included in the memory device.
    Type: Application
    Filed: June 16, 2023
    Publication date: June 20, 2024
    Inventors: Kwang Hun LEE, Ye Rin KIM, Bu Yong SONG, Jae Gwan KIM, Dong Young SEO, Won Jun CHOI
  • Publication number: 20230414483
    Abstract: The present invention provides a cosmetic composition and a preparation method therefor, the composition comprising an acryl-silicone copolymer and a diluent, wherein the diluent is a naturally occurring hydrocarbon, and the composition is prepared by removing an organic solvent through vacuum distillation carried out at a pressure of 1 torr to 500 torr and a temperature of 30° C. to 200° C. under the presence of the naturally occurring hydrocarbon.
    Type: Application
    Filed: September 28, 2021
    Publication date: December 28, 2023
    Applicant: KCC Silicone Corporation
    Inventors: Tae Ho Ko, Kwang Hun Lee, Yu Suk Jung
  • Patent number: 11734108
    Abstract: A semiconductor memory apparatus may include: a memory cell array; an ECC (Error Check and Correction) circuit configured to detect an error from data read from the memory cell array in response to a read command, correct the detected error, and output an error correction signal whenever an error is corrected; and an EF (Error Flag) generator configured to enter a flag output mode when the number of times that the error correction signal is generated during a monitoring period reaches a threshold, and output the error correction signal as an error flag in the flag output mode.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: August 22, 2023
    Assignee: SK hynix Inc.
    Inventors: Kwang Hun Lee, Ki Up Kim, Saeng Hwan Kim
  • Publication number: 20220405167
    Abstract: A semiconductor memory apparatus may include: a memory cell array; an ECC (Error Check and Correction) circuit configured to detect an error from data read from the memory cell array in response to a read command, correct the detected error, and output an error correction signal whenever an error is corrected; and an EF (Error Flag) generator configured to enter a flag output mode when the number of times that the error correction signal is generated during a monitoring period reaches a threshold, and output the error correction signal as an error flag in the flag output mode.
    Type: Application
    Filed: November 29, 2021
    Publication date: December 22, 2022
    Applicant: SK hynix Inc.
    Inventors: Kwang Hun LEE, Ki Up KIM, Saeng Hwan KIM
  • Patent number: 11062749
    Abstract: A semiconductor device includes a read control circuit configured to generate first and second output control signals including pulses which are selectively generated, from first and second strobe signals depending on burst information; and a data output circuit configured to latch first internal data depending on the pulse of the first output control signal, transfer second internal data at a time when the second output control signal level-transitions, and generate output data from the latched first internal data and the transferred second internal data.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Kwang Hun Lee, Sang Sic Yoon
  • Patent number: 11062764
    Abstract: A semiconductor device includes a control signal generation circuit and an input/output control circuit. The control signal generation circuit enters a copy operation based on a combination of logic levels of first and second operation control signals and generates a transfer control signal according to a detection result of logic levels of bits included in first internal data during the copy operation. The input/output control circuit generates first data and second data by inverting or non-inverting the logic levels of the first internal data based on the transfer control signal.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Kwang Hun Lee
  • Publication number: 20210183419
    Abstract: A semiconductor device includes a read control circuit configured to generate first and second output control signals including pulses which are selectively generated, from first and second strobe signals depending on burst information; and a data output circuit configured to latch first internal data depending on the pulse of the first output control signal, transfer second internal data at a time when the second output control signal level-transitions, and generate output data from the latched first internal data and the transferred second internal data.
    Type: Application
    Filed: June 18, 2020
    Publication date: June 17, 2021
    Applicant: SK hynix Inc.
    Inventors: Kwang Hun LEE, Sang Sic YOON
  • Patent number: 10355684
    Abstract: A calculation code generation circuit performs calibration using a counter, and a digital correction circuit including the same. The calculation code generation circuit performs a calculation process according to first and second modes, the calculation process including generating a first code by sampling a first value of the count code, generating a second code by sampling a second value of the count code, generating first and second calculation codes using the first and second codes in the first and second modes, respectively, and generating, in a calibration disable state, a third calculation code using the first and second calculation codes generated in the first and second modes, respectively, to remove the influence of the comparison offset or comparison performance of a comparator, thereby removing a calibration error.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: July 16, 2019
    Assignees: SK HYNIX INC, KUMOH NATIONAL INSTITUTE OF TECHNOLOGY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Young Chan Jang, Pil Ho Lee, Kwang Hun Lee, Hyun Bae Lee
  • Patent number: 10216239
    Abstract: A reference voltage generation circuit may be provided. The reference voltage generation circuit may be configured to generate a reference voltage according to a voltage set code. The reference voltage generation circuit may include a voltage level stabilizer. The reference voltage generation circuit may be configured to deactivate the voltage level stabilizer when a level of the reference voltage changes based on the voltage set code.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: February 26, 2019
    Assignee: SK hynix Inc.
    Inventor: Kwang Hun Lee
  • Patent number: 10211819
    Abstract: An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 19, 2019
    Assignee: SK hynix Inc.
    Inventor: Kwang Hun Lee
  • Patent number: 10116293
    Abstract: An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: October 30, 2018
    Assignee: SK hynix Inc.
    Inventor: Kwang Hun Lee
  • Publication number: 20180212597
    Abstract: An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 26, 2018
    Applicant: SK hynix Inc.
    Inventor: Kwang Hun LEE
  • Publication number: 20180183420
    Abstract: A calculation code generation circuit performs calibration using a counter, and a digital correction circuit including the same. The calculation code generation circuit performs a calculation process according to first and second modes, the calculation process including generating a first code by sampling a first value of the count code, generating a second code by sampling a second value of the count code, generating first and second calculation codes using the first and second codes in the first and second modes, respectively, and generating, in a calibration disable state, a third calculation code using the first and second calculation codes generated in the first and second modes, respectively, to remove the influence of the comparison offset or comparison performance of a comparator, thereby removing a calibration error.
    Type: Application
    Filed: July 21, 2017
    Publication date: June 28, 2018
    Inventors: Young Chan JANG, Pil Ho LEE, Kwang Hun LEE, Hyun Bae LEE
  • Patent number: 9990980
    Abstract: An internal strobe signal generating circuit may include a data rate selection circuit, a division circuit and a strobe output circuit. The data rate selection circuit may enable a data rate selection signal according to operational information. The division circuit may generate a divided strobe signal by dividing a data strobe signal in response to the data rate selection signal. The strobe output circuit may generate, in response to the data rate selection signal, an internal strobe signal based on one of the divided strobe signal and the data strobe signal.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: June 5, 2018
    Assignee: SK hynix Inc.
    Inventor: Kwang Hun Lee
  • Publication number: 20180131355
    Abstract: An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.
    Type: Application
    Filed: April 27, 2017
    Publication date: May 10, 2018
    Applicant: SK hynix Inc.
    Inventor: Kwang Hun LEE
  • Patent number: 9859884
    Abstract: A semiconductor apparatus may include a noise determination circuit, a strobe signal control circuit, and a reception circuit. The noise determination circuit may sense and determine noise of a reference voltage, and generate an up control signal and a down control signal. The strobe signal control circuit may adjust a transition timing of a strobe signal in response to the up control signal and the down control signal, and output a control strobe signal. The reception circuit may generate internal data signal in response to external data signal, the reference voltage, and the control strobe signal.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: January 2, 2018
    Assignee: SK hynix Inc.
    Inventor: Kwang Hun Lee
  • Patent number: 9859869
    Abstract: A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may generate a calibration code by performing an impedance calibration operation, and may generate a correction calibration code by inverting or maintaining logic levels of the calibration code based on the calibration code. The output circuit may generate an output signal based on an input signal and the correction calibration code.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: January 2, 2018
    Assignee: SK hynix Inc.
    Inventor: Kwang Hun Lee