Abstract: A positive electrode including a positive electrode active material layer disposed on at least one surface of a positive electrode current collector, the positive electrode active material layer including a lithium transition metal phosphate, a fluorine-based binder, and a conductive material. The lithium transition metal phosphate includes a carbon coating layer formed on a surface thereof, and a ratio (B/A) of a total weight (B) of the fluorine-based binder to a total weight (A) of carbon of the conductive material and the lithium transition metal phosphate in the positive electrode active material layer is 0.7 to 1.7.

Abstract: A wafer level package includes: a substrate; an element portion disposed on one surface of the substrate; a cap disposed on the substrate to cover the element portion; a connection portion electrically connected to the element portion; and a bonding portion disposed on an outer side of the connection portion, wherein the bonding portion is disposed on a first surface of one of the substrate and the cap, wherein one end portion of the connection portion is disposed on a second surface having a step difference from the first surface, and wherein the connection portion and the bonding portion are formed of a eutectic material.

Abstract: A display device includes a substrate including an emission area and a non-emission area, alignment electrodes arranged to be spaced from each other in a first direction on the substrate and extending in a second direction crossing the first direction, and pixels arranged along the second direction. Pixels adjacent to each other in the second direction from among the pixels may be configured to emit light of different colors. Each of the pixels may include first light emitting elements on the alignment electrodes and arranged along the second direction, second light emitting elements on the alignment electrodes, spaced from the first light emitting elements in the first direction, and arranged along the second direction, a first pixel electrode electrically connected to a first driving power and first ends of the first light emitting elements, a second pixel electrode spaced from the first pixel electrode in the first direction.

Abstract: Proposed is a dual band RFID tag including a first rectifier configured to receive and rectify a first RF signal modulated at a first frequency, a first regulator configured to regulate an output voltage of the first rectifier, a second rectifier configured to receive and rectify a second RF signal modulated at a second frequency, a second regulator configured to regulate an output voltage of the second rectifier, a voltage distributor connected to a first node and a ground in a state of being positioned therebetween, the output terminal of the first rectifier and the output terminal of the second rectifier being both connected to the first node, a multiplexer configured to output any one of an analog detection signal output from a sensor and an output signal of the voltage distributor, in response to a first selection signal or a second selection signal, and an analog-to-digital converter configured to receive as an operating voltage a voltage of a second node to which an output terminal of the first regulat

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

Abstract: Disclosed herein is an optical device for augmented reality capable of providing an expanded eyebox through polarization. The optical device for augmented reality includes: an image output unit configured to output a first virtual image light polarized in a first direction and a second virtual image light polarized in a second direction; an optical means configured to transmit real object image light therethrough to the pupil of an eye of a user; a first optical element disposed in the optical means, and configured to provide a first virtual image by transferring only the first one of the first and second virtual image lights to the pupil of the user; and a second optical element disposed in the optical means, and configured to provide a second virtual image by transferring only the second one of the first and second virtual image lights to the pupil of the user.

Abstract: An ultrasonic image providing method of the present disclosure includes: receiving ultrasonic images; measuring a plurality of similarities for a plurality of measurement items for at least one of the ultrasonic images; comparing the plurality of similarities with corresponding default thresholds, respectively; when none of the plurality of similarities is greater than the corresponding default threshold, selecting a measurement item maintaining the greatest similarity among the plurality of similarities for a reference time; and providing an ultrasonic image for the selected measurement item as an ultrasonic image.

Abstract: The present invention provides a cosmetic composition and a preparation method therefor, the composition comprising an acryl-silicone copolymer and a diluent, wherein the diluent is a naturally occurring hydrocarbon, and the composition is prepared by removing an organic solvent through vacuum distillation carried out at a pressure of 1 torr to 500 torr and a temperature of 30° C. to 200° C. under the presence of the naturally occurring hydrocarbon.

Abstract: A semiconductor memory apparatus may include: a memory cell array; an ECC (Error Check and Correction) circuit configured to detect an error from data read from the memory cell array in response to a read command, correct the detected error, and output an error correction signal whenever an error is corrected; and an EF (Error Flag) generator configured to enter a flag output mode when the number of times that the error correction signal is generated during a monitoring period reaches a threshold, and output the error correction signal as an error flag in the flag output mode.

Abstract: A semiconductor memory apparatus may include: a memory cell array; an ECC (Error Check and Correction) circuit configured to detect an error from data read from the memory cell array in response to a read command, correct the detected error, and output an error correction signal whenever an error is corrected; and an EF (Error Flag) generator configured to enter a flag output mode when the number of times that the error correction signal is generated during a monitoring period reaches a threshold, and output the error correction signal as an error flag in the flag output mode.

Abstract: A semiconductor device includes a read control circuit configured to generate first and second output control signals including pulses which are selectively generated, from first and second strobe signals depending on burst information; and a data output circuit configured to latch first internal data depending on the pulse of the first output control signal, transfer second internal data at a time when the second output control signal level-transitions, and generate output data from the latched first internal data and the transferred second internal data.

Abstract: A semiconductor device includes a control signal generation circuit and an input/output control circuit. The control signal generation circuit enters a copy operation based on a combination of logic levels of first and second operation control signals and generates a transfer control signal according to a detection result of logic levels of bits included in first internal data during the copy operation. The input/output control circuit generates first data and second data by inverting or non-inverting the logic levels of the first internal data based on the transfer control signal.

Abstract: A semiconductor device includes a read control circuit configured to generate first and second output control signals including pulses which are selectively generated, from first and second strobe signals depending on burst information; and a data output circuit configured to latch first internal data depending on the pulse of the first output control signal, transfer second internal data at a time when the second output control signal level-transitions, and generate output data from the latched first internal data and the transferred second internal data.

Abstract: A calculation code generation circuit performs calibration using a counter, and a digital correction circuit including the same. The calculation code generation circuit performs a calculation process according to first and second modes, the calculation process including generating a first code by sampling a first value of the count code, generating a second code by sampling a second value of the count code, generating first and second calculation codes using the first and second codes in the first and second modes, respectively, and generating, in a calibration disable state, a third calculation code using the first and second calculation codes generated in the first and second modes, respectively, to remove the influence of the comparison offset or comparison performance of a comparator, thereby removing a calibration error.

Abstract: A reference voltage generation circuit may be provided. The reference voltage generation circuit may be configured to generate a reference voltage according to a voltage set code. The reference voltage generation circuit may include a voltage level stabilizer. The reference voltage generation circuit may be configured to deactivate the voltage level stabilizer when a level of the reference voltage changes based on the voltage set code.

Abstract: An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.

Abstract: An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.

Abstract: An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.

Abstract: A calculation code generation circuit performs calibration using a counter, and a digital correction circuit including the same. The calculation code generation circuit performs a calculation process according to first and second modes, the calculation process including generating a first code by sampling a first value of the count code, generating a second code by sampling a second value of the count code, generating first and second calculation codes using the first and second codes in the first and second modes, respectively, and generating, in a calibration disable state, a third calculation code using the first and second calculation codes generated in the first and second modes, respectively, to remove the influence of the comparison offset or comparison performance of a comparator, thereby removing a calibration error.

Abstract: An internal strobe signal generating circuit may include a data rate selection circuit, a division circuit and a strobe output circuit. The data rate selection circuit may enable a data rate selection signal according to operational information. The division circuit may generate a divided strobe signal by dividing a data strobe signal in response to the data rate selection signal. The strobe output circuit may generate, in response to the data rate selection signal, an internal strobe signal based on one of the divided strobe signal and the data strobe signal.