Patents by Inventor Kwang-hyeon Baik

Kwang-hyeon Baik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8878211
    Abstract: Provided are a heterogeneous substrate, a nitride-based semiconductor device using the same, and a manufacturing method thereof to form a high-quality non-polar or semi-polar nitride layer on a non-polar or semi-polar plane of the heterogeneous substrate by adjusting a crystal growth mode. A base substrate having one of a non-polar plane and a semi-polar plane is prepared, and a nitride-based nucleation layer is formed on the plane of the base substrate. A first buffer layer is grown faster in the vertical direction than in the lateral direction on the nucleation layer. A lateral growth layer is grown faster in the lateral direction than in the vertical direction on the first buffer layer. A second buffer layer is formed on the lateral growth layer. A silicon nitride layer having a plurality of holes may be formed between the lateral growth layer on the first buffer layer and the second buffer layer.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: November 4, 2014
    Assignee: Korea Electronics Technology Institute
    Inventors: Sung Min Hwang, Kwang Hyeon Baik, Yong Gon Seo, Hyung Do Yoon, Jae Hyoun Park
  • Patent number: 8518723
    Abstract: A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: August 27, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chong-Kwang Chang, Hong-Jae Shin, Nae-In Lee, Kwang-Hyeon Baik, Seung-Il Bok, Hyo-Jeong Kim
  • Publication number: 20120086017
    Abstract: Provided are a heterogeneous substrate, a nitride-based semiconductor device using the same, and a manufacturing method thereof to form a high-quality non-polar or semi-polar nitride layer on a non-polar or semi-polar plane of the heterogeneous substrate by adjusting a crystal growth mode. A base substrate having one of a non-polar plane and a semi-polar plane is prepared, and a nitride-based nucleation layer is formed on the plane of the base substrate. A first buffer layer is grown faster in the vertical direction than in the lateral direction on the nucleation layer. A lateral growth layer is grown faster in the lateral direction than in the vertical direction on the first buffer layer. A second buffer layer is formed on the lateral growth layer. A silicon nitride layer having a plurality of holes may be formed between the lateral growth layer on the first buffer layer and the second buffer layer.
    Type: Application
    Filed: December 15, 2011
    Publication date: April 12, 2012
    Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
    Inventors: Sung Min HWANG, Kwang Hyeon BAIK, Yong Gon SEO, Hyung Do YOON, Jae Hyoun PARK
  • Patent number: 8013354
    Abstract: A semiconductor light emitting device having a multiple pattern structure greatly increases light extraction efficiency. The semiconductor light emitting device includes a substrate and a semiconductor layer, an active layer, and an electrode layer formed on the substrate, a first pattern defining a first corrugated structure between the substrate and the semiconductor layer, and a second pattern defining a second corrugated structure on the first corrugated structure of the first pattern.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: September 6, 2011
    Assignees: Samsung LED Co., Ltd., Seoul National University Industry Foundation
    Inventors: Jeong-wook Lee, Jin-seo Im, Bok-ki Min, Kwang-hyeon Baik, Heon-su Jeon
  • Patent number: 7989244
    Abstract: Provided is a method of manufacturing a nitride-based semiconductor light-emitting device having increased efficiency and increased output properties. The method may include forming a sacrificial layer having a wet etching property on a substrate, forming a protective layer on the sacrificial layer, protecting the sacrificial layer in a reaction gas atmosphere for crystal growth, and facilitating epitaxial growth of a semiconductor layer to be formed on the protective layer, forming a semiconductor device including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the protective layer, and removing the substrate from the semiconductor device by wet etching the sacrificial layer.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: August 2, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Kyoung-kook Kim, Kwang-ki Choi, June-o Song, Suk-ho Yoon, Kwang-hyeon Baik, Hyun-soo Kim
  • Publication number: 20100136790
    Abstract: A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.
    Type: Application
    Filed: November 23, 2009
    Publication date: June 3, 2010
    Inventors: Chong-Kwang Chang, Hong-Jae Shin, Nae-In Lee, Kwang-Hyeon Baik, Seung-Il Bok, Hyo-Jeong Kim
  • Publication number: 20090095981
    Abstract: Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. The CMOS device comprises an epi-layer that may be formed on a substrate; a first semiconductor layer and a second semiconductor layer that may be formed on different regions of the epi-layer, respectively; and a PMOS transistor and a NMOS transistor that may be formed on the first and second semiconductor layers, respectively.
    Type: Application
    Filed: March 4, 2008
    Publication date: April 16, 2009
    Inventors: Dong-hun Kang, Sang-moon Lee, Joong S. Jeong, Kwang-hyeon Baik
  • Publication number: 20080038857
    Abstract: Provided is a method of manufacturing a nitride-based semiconductor light-emitting device having increased efficiency and increased output properties. The method may include forming a sacrificial layer having a wet etching property on a substrate, forming a protective layer on the sacrificial layer, protecting the sacrificial layer in a reaction gas atmosphere for crystal growth, and facilitating epitaxial growth of a semiconductor layer to be formed on the protective layer, forming a semiconductor device including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the protective layer, and removing the substrate from the semiconductor device by wet etching the sacrificial layer.
    Type: Application
    Filed: May 23, 2007
    Publication date: February 14, 2008
    Inventors: Kyoung-kook Kim, Kwang-ki Choi, June-o Song, Suk-ho Yoon, Kwang-hyeon Baik, Hyun-soo Kim
  • Publication number: 20070262330
    Abstract: A semiconductor light emitting device having a multiple pattern structure greatly increases light extraction efficiency. The semiconductor light emitting device includes a substrate and a semiconductor layer, an active layer, and an electrode layer formed on the substrate, a first pattern defining a first corrugated structure between the substrate and the semiconductor layer, and a second pattern defining a second corrugated structure on the first corrugated structure of the first pattern.
    Type: Application
    Filed: April 19, 2007
    Publication date: November 15, 2007
    Applicants: SAMSUNG ELECTRO-MECHANICS CO., LTD., SEOUL NATIONAL UNIVERSITY INDUSTRY FOUNDATION
    Inventors: Jeong-wook LEE, Jin-seo IM, Bok-ki MIN, Kwang-hyeon BAIK, Heon-su JEON