Abstract: An error correction circuit using a BCH code may include a decoder performing at least one of a first error correction decoding using a first error correction capability or a second error correction decoding using a second error correction capability and an encoder generating a codeword based on a message and a generation matrix corresponding to the first error correction capability and generating an additional parity based on the codeword and one or more rows of a parity check matrix corresponding to the second error correction capability, wherein a syndrome vector generated based on a read vector corresponding to the codeword is used during the first error correction decoding and an additional syndrome generated based on the additional parity is used during the second error correction decoding, and wherein the one or more rows are extended from a parity check matrix corresponding to the first error correction capability.

Abstract: A method of manufacturing a photo sensor includes forming a first conductive layer on a substrate, the first conductive layer including a metal layer and a transparent conductive oxide layer formed on the metal layer, forming a photoconductive layer on the first conductive layer, forming a second conductive layer on the photoconductive layer, forming a first photoresist pattern on the second conductive layer, etching the second conductive layer using the first photoresist pattern as an etch mask to form a second electrode, deforming the first photoresist pattern to form a second photoresist pattern, and etching the photoconductive layer and the first conductive layer using the second photoresist pattern to form a photoconductive pattern and a first electrode, respectively.

Abstract: Provided herein may be an error correction circuit, and a memory controller and a memory system. The error correction circuit may include an encoder configured to generate a codeword comprising a message part, a first parity part, and a second parity part, and a decoder configured to perform error correction decoding using read values corresponding to at least a portion of the codeword, wherein, the decoder is configured to perform error correction decoding based on a first or a second error correction ability such that error correction decoding using the first error correction ability is performed using partial read values corresponding to a partial codeword including the message part and the first parity part, and error correction decoding using the second error correction ability is performed using read values corresponding to the entire codeword, and wherein the second error correction ability is greater than the first error correction ability.

Abstract: A display device includes: a first semiconductor layer on a first buffer layer, and including a first active layer; a first gate insulating layer on the first semiconductor layer, and covering the first active layer; a first conductive layer on the first gate insulating layer, and including a first gate electrode; a second conductive layer on the first conductive layer, and including a first source/drain electrode; a first interlayer insulating layer on the first conductive layer; a second semiconductor layer on the first interlayer insulating layer, and including a second active layer; a second gate insulating layer on the second semiconductor layer, and covering the second active layer; and a third conductive layer on the second gate insulating layer, and including a second gate electrode and a second source/drain electrode. The first gate insulating layer and the second gate insulating layer include different insulating materials from each other.

Abstract: A common memory device shared by a first processor and a second processor is provided. The common memory device includes a memory cell array including a first memory region allocated for the first processor and a second memory region allocated for the second processor, a refresh masking information storage circuit configured to store refresh masking information indicating whether a refresh is performed on at least one of the first and second memory regions, and a refresh circuit configured to selectively perform the refresh on the first memory region and the second memory region according to the refresh masking information.

Abstract: A membrane apparatus including a housing, a forward osmosis membrane dividing an internal space of the housing into an inlet region and a mixing region, and a pervaporation membrane dividing the internal space of the housing into the mixing region and a discharge region. The forward osmosis membrane separates a preliminary filtration liquid from an inlet liquid and provides the separated preliminary filtration liquid to the mixing region, the preliminary filtration liquid is mixed with a forward osmosis draw solution to make a mixed solution, the pervaporation membrane separates a final filtration liquid from the mixed solution and provides the separated final filtration liquid to the discharge region, the final filtration liquid is vaporized in the discharge region to make vapor, and an amount of the vapor is adjusted by at least one of a temperature of the mixed solution and a degree of vacuum of the discharge region.

Abstract: An error correction circuit using a BCH code may include a decoder performing at least one of a first error correction decoding using a first error correction capability or a second error correction decoding using a second error correction capability and an encoder generating a codeword based on a message and a generation matrix corresponding to the first error correction capability and generating an additional parity based on the codeword and one or more rows of a parity check matrix corresponding to the second error correction capability, wherein a syndrome vector generated based on a read vector corresponding to the codeword is used during the first error correction decoding and an additional syndrome generated based on the additional parity is used during the second error correction decoding, and wherein the one or more rows are extended from a parity check matrix corresponding to the first error correction capability.

Abstract: Provided are a dynamic semiconductor memory device and a memory system including the same.

Abstract: The present invention relates to a pharmaceutical composition for preventing or treating respiratory disease, which comprises an alcohol or organic solvent extract of Justicia procumbens L. as an active ingredient, and to a pharmaceutical composition for preventing or treating respiratory disease, which comprises an alcohol or organic solvent extract of Justicia procumbens L., the extract comprising any one or more of justicidin A, justicidin B, justicidin C and phyllamyricin C, and also to a food composition for preventing or treating respiratory disease, which comprises the alcohol or organic solvent extract. The composition comprising the Justicia procumbens L. extract according to the present invention may inhibit abnormal overproliferation of splenocytes, may inhibit the secretion of allergic inflammatory cytokines, and exhibits an expectorant effect and an airway constriction inhibitory effect. Thus, it may effectively prevent, treat or improve respiratory disease.

Abstract: Provided are an anode for electrolysis, which includes a metal base, and a catalyst layer disposed on at least one surface of the metal base, wherein the catalyst layer includes a composite metal oxide of ruthenium, iridium, titanium, and platinum, and a metal in the composite metal oxide does not include palladium, wherein, when the catalyst layer is equally divided into a plurality of pixels, a standard deviation of iridium compositions of the plurality of equally divided pixels is 0.40 or less, and a method of preparing the same.

Abstract: The present invention relates to a pharmaceutical composition, food composition and cosmetic composition for preventing, treating, or improving allergic diseases comprising extract or fraction of a plant of the Justicia genus as an active ingredient. The extract or a fraction of a plant of the Justicia genus according to the present invention can inhibit IgE antibody secretion and the degranulation of mast cells and basophils, and exhibits an excellent anti-allergic effect, and thus can effectively prevent, treat, or improve allergic diseases.

Abstract: Provided are a dynamic semiconductor memory device and a memory system including the same.

Abstract: Provided herein may be an error correction circuit, and a memory controller and a memory system. The error correction circuit may include an encoder configured to generate a codeword comprising a message part, a first parity part, and a second parity part, and a decoder configured to perform error correction decoding using read values corresponding to at least a portion of the codeword, wherein, the decoder is configured to perform error correction decoding based on a first or a second error correction ability such that error correction decoding using the first error correction ability is performed using partial read values corresponding to a partial codeword including the message part and the first parity part, and error correction decoding using the second error correction ability is performed using read values corresponding to the entire codeword, and wherein the second error correction ability is greater than the first error correction ability.

Abstract: An error correction circuit includes a decoder including a plurality of check node units and variable node units corresponding to a parity check matrix of low density parity check (LDPC) scheme, and configured to generate decoded data by decoding a codeword; a syndrome check circuit configured to calculate a reference value for the codeword based on the parity check matrix, and generate a decoder operation control signal corresponding to the reference value; and a control circuit configured to control whether to operate each of the plurality of check node units and variable node units of the decoder in response to the decoder operation control signal, wherein the decoder decodes the codeword based on check node units and variable node units which operate according to the control of the control circuit among the plurality of check node units and variable node units.

Abstract: An organic light-emitting display device has improved transmittance and UV light reliability by optimizing the thickness and material of a cathode. An organic light-emitting display device comprises an organic light-emitting element on a substrate, the organic light-emitting element including an anode, an organic light emitting layer, and a cathode, an organic layer between the substrate and the organic light-emitting element, and an auxiliary layer adjacent to the cathode and including a material having electron injection ability, such that the influence of UV lights on the OLED device is reduced, thereby improving the efficiency and lifespan of the organic light-emitting element.

Abstract: A method for operating a data storage device includes providing a nonvolatile memory device including a page divided into a first half page and a second half page; dividing, when receiving data smaller than a size of a page, the data into first and second partial data; generating first and second valid data by adding metadata to the first and second partial data; generating first dummy data to be stored in the first half page together with the first valid data and second dummy data to be stored in the second half page together with the second valid data; storing the first valid data in the first half page and the second valid data in the second half page such that the first and second valid data are successive; and storing the first dummy data in an unused area of the first half page and the second dummy data in an unused area of the second half page.

Abstract: A method of manufacturing a display device, including: providing a display element layer on a substrate; forming a thin film encapsulation layer covering the display element layer; aging the thin film encapsulation layer by using a light source emitting artificial sunlight; and forming a window on the aged thin film encapsulation layer.

Abstract: A method of manufacturing a display device, including: providing a display element layer on a substrate; forming a thin film encapsulation layer covering the display element layer; aging the thin film encapsulation layer by using a light source emitting artificial sunlight; and forming a window on the aged thin film encapsulation layer.

Abstract: A common memory device shared by a first processor and a second processor is provided. The common memory device includes a memory cell array including a first memory region allocated for the first processor and a second memory region allocated for the second processor, a refresh masking information storage circuit configured to store refresh masking information indicating whether a refresh is performed on at least one of the first and second memory regions, and a refresh circuit configured to selectively perform the refresh on the first memory region and the second memory region according to the refresh masking information.

Abstract: An error correction circuit includes a decoder including a plurality of check node units and variable node units corresponding to a parity check matrix of low density parity check (LDPC) scheme, and configured to generate decoded data by decoding a codeword; a syndrome check circuit configured to calculate a reference value for the codeword based on the parity check matrix, and generate a decoder operation control signal corresponding to the reference value; and a control circuit configured to control whether to operate each of the plurality of check node units and variable node units of the decoder in response to the decoder operation control signal, wherein the decoder decodes the codeword based on check node units and variable node units which operate according to the control of the control circuit among the plurality of check node units and variable node units.