Abstract: An electronic system includes a host device and a storage device including a first memory device of a volatile type and a second memory device of a nonvolatile type. The first memory device is accessed by the host device through a memory-mapped input-output interface and the second memory device is accessed by the host device through a block accessible interface. The storage device provides a virtual memory region to the host device such that a host-dedicated memory region having a first size included in the first memory device is mapped to the virtual memory region having a second size larger than the first size.

Abstract: An electronic system includes a host device and a storage device including a first memory device of a volatile type and a second memory device of a nonvolatile type. The first memory device is accessed by the host device through a memory-mapped input-output interface and the second memory device is accessed by the host device through a block accessible interface. The storage device provides a virtual memory region to the host device such that a host-dedicated memory region having a first size included in the first memory device is mapped to the virtual memory region having a second size larger than the first size.

Abstract: A method for operating a semiconductor device includes obtaining task structure information of a task processed in a multiprocessor system. The multiprocessor system includes a plurality of nodes, each comprising one or more processing units and a memory directly connected to the processing units. The plurality of nodes include a local node to which an input/output (I/O) device is directly connected and a remote node having no direct connection to the I/O device. The method further includes evaluating the task structure information to determine whether the task is an I/O intensive task and assigning the task to the local node if the task is evaluated to be the I/O intensive task.

Abstract: A flexible server system includes an embedded processor, one or more processor boards, one or more storage boards, and a switch including a plurality of ports. The embedded processor, the one or more processor boards, and the one or more storage boards are connected to a corresponding one of the plurality of ports. The embedded processor, the one or more processor boards, the one or more storage boards, and the switch each include a peripheral component interconnect express (PCIe) interface. The one or more processor boards and the one or more storage boards are connected to the switch through connectors where each of the corresponding connectors have a same size. The embedded processor controls the switch to route a packet from one of the plurality of ports to another one of the plurality of ports.

Abstract: Provided is a method for handling interrupts. The method includes receiving a first interrupt, and allocating the first interrupt to a first task queue of a first processing unit among a plurality of processing units, receiving a second interrupt, and allocating the second interrupt to the first task queue, handling the first interrupt allocated to the first task queue on the first processing unit, selecting a second processing unit that will handle the second interrupt among the plurality of processing units while the first interrupt is handled, and transferring the second interrupt allocated to the first task queue to a second task queue of the selected second processing unit.

Abstract: A flexible server system includes an embedded processor, one or more processor boards, one or more storage boards, and a switch including a plurality of ports. The embedded processor, the one or more processor boards, and the one or more storage boards are connected to a corresponding one of the plurality of ports. The embedded processor, the one or more processor boards, the one or more storage boards, and the switch each include a peripheral component interconnect express (PCIe) interface. The one or more processor boards and the one or more storage boards are connected to the switch through connectors where each of the corresponding connectors have a same size. The embedded processor controls the switch to route a packet from one of the plurality of ports to another one of the plurality of ports.

Abstract: A semiconductor apparatus and system are provided. The semiconductor apparatus includes a host core configured to drive at least one device drive and a solid state drive (SSD), a flash interface configured to interface with the host core and the SSD, and an internal bus configured to transmit signals between the host core and the flash interface, wherein the host core, the flash interface, and the internal bus are disposed on a single chip substrate, and the SSD is not disposed on the single chip substrate.

Abstract: Provided is an apparatus and method for automatically extracting an interface of embedded software. The method defines an interface of embedded software as a test item for test of the interface of the embedded software, and generates an interface symbol corresponding to the defined test item. The location of the interface symbol is determined, and a test case is generated based on the interface symbol and its location in the software. Embodiments of the invention thus facilitate the testing of software at interfaces between layers in the software.

Abstract: Embodiments of the invention provide a device and a method for automatically testing embedded software, and more specifically for testing interfaces between layers of the embedded software. In one embodiment, the device includes: an emulator; a server including embedded software; an evaluation board configured to download the embedded software from the server and controlled by the emulator; and a host system configured to receive the embedded software from the server and automatically generate test cases for testing the embedded software using the emulator.

Abstract: Embodiments of the invention provide a device and a method for automatically testing embedded software, and more specifically for testing interfaces between layers of the embedded software. In one embodiment, the device includes: an emulator; a server including embedded software; an evaluation board configured to download the embedded software from the server and controlled by the emulator; and a host system configured to receive the embedded software from the server and automatically generate test cases for testing the embedded software using the emulator.

Abstract: Provided is an apparatus and method for automatically extracting an interface of embedded software. The method defines an interface of embedded software as a test item for test of the interface of the embedded software, and generates an interface symbol corresponding to the defined test item. The location of the interface symbol is determined, and a test case is generated based on the interface symbol and its location in the software. Embodiments of the invention thus facilitate the testing of software at interfaces between layers in the software.

Abstract: A liquid crystal display device includes dual bank type source driver PCBs installed at the top and the bottom of a liquid crystal panel, a gate driver PCB, and a staple-shaped main PCB formed in a body with a top portion and a bottom portion proceeding in the horizontal direction and a side portion proceeding in the vertical direction. The top portion and the bottom portion of the main PCB axially meet the side portion of the main PCB at a predetermined angle. A timing controller is mounted at the main PCB to process signals input from outside and generate driving signals. The main PCB transmits the relevant driving signals to the respective source driver PCBs and the gate driver PCB.

Abstract: The present invention is directed to a flat panel display device and a method for driving thereof. According to the present invention, in the flat panel display for processing and displaying a display signal outputted from the graphic source via a serial bus, the graphic source fetches and interprets the display characteristics information of the flat panel display from the flat panel display module via the serial bus so that a new corresponding standard of display signal can be outputted. Here, the display characteristics information is adjustable by the input of predetermined data by use of a predetermined key installed outside the flat panel display by a user and includes more than one of standard information of the display signal with its blanking interval defined and screen display information.

Abstract: The present invention relates to a liquid crystal display with two or more line inversion. The timing controller of the liquid crystal display controls polarity of the image data to be reversed every two or more rows, combines the image data for the pixels with the polarity inversion and compensation data for excessive charging of the pixels by a predetermined level, and outputs the combined data. For this purpose, the timing controller includes a vector table for storing the number of frames and lines to be compensated for a frequency of a clock signal, a frame frequency, and a line frequency. In order to apply voltages for excessive charging of the pixel with polarity inversion, the compensation data stored in the vector table is combined with the image data from the external graphics source, and the liquid crystal panel is driven using the combined data.

Abstract: A liquid crystal display device includes dual bank type source driver PCBs installed at the top and the bottom of a liquid crystal panel, a gate driver PCB, and a staple-shaped main PCB formed in a body with a top portion and a bottom portion proceeding in the horizontal direction and a side portion proceeding in the vertical direction. The top portion and the bottom portion of the main PCB axially meet the side portion of the main PCB at a predetermined angle. A timing controller is mounted at the main PCB to process signals input from outside and generate driving signals. The main PCB transmits the relevant driving signals to the respective source driver PCBs and the gate driver PCB.

Abstract: In an active matrix display device, gate signals are delayed or distorted as they go to the right due to load of the gate lines and parasitic capacitances of the gate lines and pixels. TP signals for respective blocks of data lines are supplied with time difference such that data signals are applied to the respective blocks of the data lines not in synchronous manner but in a staggered manner. The time difference in the application of the data signals between the data lines is substantially equal to the delay of the gate signals, thereby solving the non-uniform charging of the data signals in the pixels.

Abstract: A liquid crystal display device includes dual bank type source driver PCBs installed at the top and the bottom of a liquid crystal panel, a gate driver PCB, and a staple-shaped main PCB formed in a body with a top portion and a bottom portion proceeding in the horizontal direction and a side portion proceeding in the vertical direction. The top portion and the bottom portion of the main PCB axially meet the side portion of the main PCB at a predetermined angle. A timing controller is mounted at the main PCB to process signals input from outside and generate driving signals. The main PCB transmits the relevant driving signals to the respective source driver PCBs and the gate driver PCB.

Abstract: The present invention is directed to a flat panel display device and a method for driving thereof. According to the present invention, in the flat panel display for processing and displaying a display signal outputted from the graphic source via a serial bus, the graphic source fetches and interprets the display characteristics information of the flat panel display from the flat panel display module via the serial bus so that a new corresponding standard of display signal can be outputted. Here, the display characteristics information is adjustable by the input of predetermined data by use of a predetermined key installed outside the flat panel display by a user and includes more than one of standard information of the display signal with its blanking interval defined and screen display information.

Abstract: A liquid crystal display device includes dual bank type source driver PCBs installed at the top and the bottom of a liquid crystal panel, a gate driver PCB, and a staple-shaped main PCB formed in a body with a top portion and a bottom portion proceeding in the horizontal direction and a side portion proceeding in the vertical direction. The top portion and the bottom portion of the main PCB axially meet the side portion of the main PCB at a predetermined angle. A timing controller is mounted at the main PCB to process signals input from outside and generate driving signals. The main PCB transmits the relevant driving signals to the respective source driver PCBs and the gate driver PCB.