Abstract: An image sensor chip includes a first wafer and a second wafer. The first wafer includes an image sensor having a plurality of sub-pixels, each of which is configured to detect at least one photon and output a sub-pixel signal according to a result of the detection. The image processor is configured to process sub-pixel signals for each sub-pixel and generate image data. The first wafer and the second wafer are formed in a wafer stack structure.

Abstract: Provided are a dummy terminal and a main body using wireless communication. The dummy terminal obtains speech information from a user, receives at least one of video information and audio information from the main body through short-distance wireless communication, transmits the obtained speech information to the main body, and changes at least one of the received video information and audio information to output the changed information through a display unit and/or a speaker unit.

Abstract: A correlated double sampling (CDS) circuit may include a sampling circuit and a switching circuit. The CDS circuit may perform a CDS operation on a reset component of an input signal and an image component of the input signal based on a ramp signal, and the CDS circuit may generate an output signal. The switching circuit may include an auto-zero switch that connects a first input terminal receiving the input signal to an output node in response to an auto-zero control signal during an auto-zero interval. The switching circuit may connect a first terminal of the auto-zero switch to a reference voltage in order to cutoff a leakage current flowing to the auto-zero switch in response to a first boosting control signal during a first comparison interval and a second comparison interval. The output signal may be provided at the output node.

Abstract: An image sensor senses object information and converts the sensed object information into an electrical signal. An image processing apparatus uses the image sensor. The image sensor includes a column signal line connected to output terminals of a plurality of pixel sensors, a comparator circuit configured to output a signal corresponding to a comparison result of a signal output to the column signal line and a reference signal, an ADC circuit configured to convert an analog signal corresponding to an optical signal sensed by the pixel sensor selected from the plurality of pixel sensors connected to the column signal line into digital data based on the signal output from the comparator circuit and, a load circuit connected in series to the comparator circuit between the column signal line and a ground terminal, wherein the load circuit is configured as a common load device of the plurality of pixel sensors connected to the column signal line and the comparator circuit.

Abstract: An image sensor includes a pixel array and a row driver block. The pixel array includes a plurality of subpixel groups, each including a plurality of subpixels. Each of the plurality of subpixels is configured to generate a subpixel signal corresponding to photocharge accumulated in response to a photon. The row driver block is configured to generate a first control signal to control the subpixels included in each of the plurality of subpixel groups to accumulate the photocharge in parallel from a first time point to a second time point.

Abstract: Disclosed herein are a server duplication system and method and a storage medium storing a server duplication computer program. The server duplication system includes a primary server including a hypervisor including a hypervisor-based fault tolerance module and a first file system virtual machine (FS VM), and a first standby server including a hypervisor including a hypervisor-based fault tolerance module that exchanges data with a fault tolerance module provided on the hypervisor of the primary server and duplicates the primary server. The first FS VM provides a first file system that is shared by a user virtual machine (USER VM), and a buffer cache that is used in conjunction with the first file system is provided on virtual memory. The first FS VM is duplicated into the standby server using the hypervisor-based fault tolerance module of the primary server and the hypervisor-based fault tolerance module of the standby server.

Abstract: A wireless communication node device is provided. The node device includes a network adaptor configured to perform short-range wireless communication, a channel manager configured to receive channel setting information comprising information about channel member nodes through the network adaptor, and to store the received channel setting information, a channel state manager configured to update a channel state table which indicates that the node device is connected to another node device, in response to the node device being connected to the other node device through the network adaptor, and to propagate the updated connection state table via the network adaptor, and an alarm controller configured to verify a connection state between the channel member nodes by analyzing the connection state table, and to generate an alarm control signal based on the verified connection state.

Abstract: An image sensor senses object information and converts the sensed object information into an electrical signal. An image processing apparatus uses the image sensor. The image sensor includes a column signal line connected to output terminals of a plurality of pixel sensors, a comparator circuit configured to output a signal corresponding to a comparison result of a signal output to the column signal line and a reference signal, an ADC circuit configured to convert an analog signal corresponding to an optical signal sensed by the pixel sensor selected from the plurality of pixel sensors connected to the column signal line into digital data based on the signal output from the comparator circuit and, a load circuit connected in series to the comparator circuit between the column signal line and a ground terminal, wherein the load circuit is configured as a common load device of the plurality of pixel sensors connected to the column signal line and the comparator circuit.

Abstract: ACMOS image sensor includes a pixel array having a plurality of pixels. Each of the plurality of pixels includes: a photogate structure configured to be controlled based on a first gate voltage; and a sensing transistor including a charge pocket region formed in a substrate region, the sensing transistor being configured to be controlled based on a second gate voltage. Based on the first gate voltage, the photogate structure is configured to integrate charges generated in response to light incident on the substrate region. The sensing transistor is configured to adjust at least one of a threshold voltage of the sensing transistor and a current flow in the sensing transistor according to charges transferred from the photogate structure to the charge pocket region based on a difference between the first gate voltage and the second gate voltage.

Abstract: There are provided a power conversion mode control apparatus of a bi-directional DC-DC converter including: a controlling unit determining an overall reference current so as to perform a power conversion from a side in which an actual voltage is relatively larger than a reference voltage to a side in which the actual voltage is relatively smaller than the reference voltage by comparing a voltage error of low voltage side and a voltage error of high voltage side with each other; and a duty command generating unit generating duty command based on a difference between the overall reference current and a current of low voltage side and providing the duty command to the bi-directional DC-DC converter.

Abstract: An image sensor senses object information and converts the sensed object information into an electrical signal. An image processing apparatus uses the image sensor. The image sensor includes a column signal line connected to output terminals of a plurality of pixel sensors, a comparator circuit configured to output a signal corresponding to a comparison result of a signal output to the column signal line and a reference signal, an ADC circuit configured to convert an analog signal corresponding to an optical signal sensed by the pixel sensor selected from the plurality of pixel sensors connected to the column signal line into digital data based on the signal output from the comparator circuit and, a load circuit connected in series to the comparator circuit between the column signal line and a ground terminal, wherein the load circuit is configured as a common load device of the plurality of pixel sensors connected to the column signal line and the comparator circuit.

Abstract: A binary complementary metal-oxide-semiconductor (CMOS) image sensor includes a pixel array and a readout circuit. The pixel array includes at least one pixel having a plurality of sub-pixels. The readout circuit is configured to quantize a pixel signal output from the pixel using a reference signal. The pixel signal corresponds to sub-pixel signals output from sub-pixels, from among the plurality of sub-pixels, activated in response to incident light.

Abstract: An image sensor according to an example embodiment concepts includes a pixel array including pixels, and each of the pixels includes photoelectric conversion elements. The photoelectric conversion elements independently operating to detect a phase difference. The image sensor further includes a control circuit configured to independently control exposure times of each of the photoelectric conversion elements included in each of the pixels.

Abstract: According to example embodiments, a photodiode includes a photoelectric layer on a first electrode, a second electrode on the photoelectric layer, and a first phosphorescence layer on the second electrode.

Abstract: A correlated double sampling (CDS) circuit may include a sampling circuit and a switching circuit. The CDS circuit may perform a CDS operation on a reset component of an input signal and an image component of the input signal based on a ramp signal, and the CDS circuit may generate an output signal. The switching circuit may include an auto-zero switch that connects a first input terminal receiving the input signal to an output node in response to an auto-zero control signal during an auto-zero interval. The switching circuit may connect a first terminal of the auto-zero switch to a reference voltage in order to cutoff a leakage current flowing to the auto-zero switch in response to a first boosting control signal during a first comparison interval and a second comparison interval. The output signal may be provided at the output node.

Abstract: An image sensor includes a pixel array in which a plurality of pixels, first and second row selection lines separated from each other, and first and second column lines separated from each other are disposed and a column selecting circuit configured to connect the first and second column lines using a column selection signal. The pixel array includes a first pixel which is connected to the first row selection line and the first column line and a second pixel which is disposed in the same row as the first pixel and connected to the second row selection line and the second column line.

Abstract: Provided are a dummy terminal and a main body using wireless communication. The dummy terminal obtains speech information from a user, receives at least one of video information and audio information from the main body through short-distance wireless communication, transmits the obtained speech information to the main body, and changes at least one of the received video information and audio information to output the changed information through a display unit and/or a speaker unit.

Abstract: An image sensor includes a sampling circuit, which is responsive to ramp and input signals provided by a pixel array. The sampling circuit is configured to perform a correlated double sampling (CDS) operation on a reset component of the input signal and an image component of the input signal. A reset circuit is also provided, which is configured to reset an output signal generated by the sampling circuit to a first level in response to a reset control signal. This reset control signal can be active during at least one of a first reset interval and a second reset interval. The first reset interval precedes a first comparison interval during which a first comparison operation is performed on the ramp signal and the reset component. The second reset interval precedes a second comparison interval during which a second comparison operation is performed on the ramp signal and the image component.

Abstract: A photonic device is provided. The photonic device includes: a semiconductor layer including first and second regions; an insulating layer covering the semiconductor layer; and first and second plugs extending to pass through the insulating layer and electrically connected to the corresponding first and second regions. The first plug is in a rectifying contact with the first region, and the second plug is in an ohmic contact with the second region.

Abstract: Disclosed herein are a server duplication system and method and a storage medium storing a server duplication computer program. The server duplication system includes a primary server including a hypervisor including a hypervisor-based fault tolerance module and a first file system virtual machine (FS VM), and a first standby server including a hypervisor including a hypervisor-based fault tolerance module that exchanges data with a fault tolerance module provided on the hypervisor of the primary server and duplicates the primary server. The first FS VM provides a first file system that is shared by a user virtual machine (USER VM), and a buffer cache that is used in conjunction with the first file system is provided on virtual memory. The first FS VM is duplicated into the standby server using the hypervisor-based fault tolerance module of the primary server and the hypervisor-based fault tolerance module of the standby server.