Patents by Inventor Kwang-Lae Cho

Kwang-Lae Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050263848
    Abstract: A metal-insulator-metal (MIM) capacitor having a large capacitance, and a method of manufacturing the same, includes forming a lower electrode on a semiconductor substrate, sequentially forming a first dielectric film, an intermediary electrode, and a second dielectric film on an upper surface of the lower electrode, forming an inter-metal insulating layer on an upper surface of the second dielectric film, etching predetermined portions of the inter-metal insulating layer to form an upper electrode region and via hole regions, selectively etching the second dielectric film exposed in a portion of the via hole regions to expose the intermediary electrode, and forming a metal layer on the upper electrode region and the via hole regions, thereby forming an upper electrode and contact plugs.
    Type: Application
    Filed: April 4, 2005
    Publication date: December 1, 2005
    Inventor: Kwang-lae Cho
  • Patent number: 6882585
    Abstract: Disclosed is a ROM device with a repair function where defective cells are repaired by a bit cell unit. The defective cells are repaired using a ground or operating (e.g., a supply) voltage line incorporated in the ROM device. This allows the defective cells to be repaired without separate redundant cells. After repairing, a test operation for replaced cells is not needed.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: April 19, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Lae Cho, Boo-Yung Huh, Seong-Ho Jeung
  • Publication number: 20040037122
    Abstract: Disclosed is a ROM device with a repair function where defective cells are repaired by a bit cell unit. The defective cells are repaired using a ground or operating (e.g., a supply) voltage line incorporated in the ROM device. This allows the defective cells to be repaired without separate redundant cells. After repairing, a test operation for replaced cells is not needed.
    Type: Application
    Filed: June 24, 2003
    Publication date: February 26, 2004
    Inventors: Kwang-Lae Cho, Boo-Yung Huh, Seong-Ho Jeung
  • Patent number: 6001719
    Abstract: Methods of forming metal silicide layers include the steps of forming electrically conductive lines that comprise the steps of forming a layer of polysilicon on a semiconductor substrate and then forming a layer of metal silicide on the polysilicon layer, opposite the substrate. The layer of metal silicide and the layer of polysilicon are then patterned as an electrically conductive line having sidewalls. The semiconductor substrate is then exposed to a cleaning agent that selectively etches the patterned layer of metal silicide at a faster rate than the patterned layer of polysilicon. The patterned layer of metal silicide is then thermally oxidized to define recess spacers extending adjacent sidewalls of the electrically conductive line. An electrically insulating layer is then formed on the electrically conductive line and on the recess spacers. The electrically insulating layer is then anisotropically etched to define insulating spacers on the recess spacers.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: December 14, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-lae Cho, Jin-gyoo Choi