Abstract: A semiconductor device package includes a substrate, a semiconductor device, and an underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.

Abstract: The present disclosure relates to a semiconductor device package comprising a substrate, a semiconductor device, and a underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.

Abstract: A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.

Abstract: A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is disposed on the substrate. The encapsulant covers the semiconductor element. The adhesion layer is disposed on the encapsulant. The metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.

Abstract: A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is disposed on the substrate. The encapsulant covers the semiconductor element. The adhesion layer is disposed on the encapsulant. The metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.

Abstract: A lead-free solder composition includes tin, titanium and zinc. Based on 100 parts by weight of the total weight of tin, titanium and zinc, tin is present in an amount ranging from 20 to 40 parts by weight, and titanium is present in an amount ranging from 0.01 to 0.15 parts by weight.

Abstract: A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.

Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor die, a semiconductor element and a solder layer. The semiconductor die includes a copper pillar. The semiconductor element includes a surface finish layer, wherein the material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of at least two of copper, nickel and tin. The second IMC is a combination of gold and tin, a combination of palladium and tin, or both.

Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor die, a semiconductor element and a solder layer. The semiconductor die includes a copper pillar. The semiconductor element includes a surface finish layer, wherein the material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of at least two of copper, nickel and tin. The second IMC is a combination of gold and tin, a combination of palladium and tin, or both.

Abstract: This invention discloses a lead-free Sn—Zn—Al—Ag solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, and the balance of Sn; and a lead-free Sn—Zn—Al—Ag—Ga solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, up to 4.0 wt % of Ga; and the balance of Sn. The lead-free solder alloys of the present invention have better tensile strength and elongation than the conventional Sn—Pb solder alloys. In addition, the lead-free solder alloys of the present invention have a melting point lower than 200° C., which is close to the 183.5° C. of an eutectic Sn—Pb alloy.

Abstract: This invention discloses a lead-free Sn—Zn—Al—Ag solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, and the balance of Sn; and a lead-free Sn—Zn—Al—Ag—Ga solder alloy, which is composed of 7-10 wt % of Zn, up to 0.5 wt % of Al, up to 4.0 wt % of Ag, up to 4.0 wt % of Ga; and the balance of Sn. The lead-free solder alloys of the present invention have better tensile strength and elongation than the conventional Sn—Pb solder alloys. In addition, the lead-free solder alloys of the present invention have a melting point lower than 200° C., which is close to the 183.5° C. of an eutectic Sn—Pb alloy.

Abstract: A process for producing solder bumps on metal electrodes, such as Al electrodes, of a semiconductor wafer, such as silicon wafer, involves the formation of the under bump metallurgies (UBM) on the electrodes. The solder bumps are then formed on the under bump metallurgies by wave soldering. The under bump metallurgies consist of a diffusion barrier layer formed on the metal electrodes, and a wetting layer formed on the diffusion barrier layer.

Abstract: A process for preparing a solder bump can be prepared by the following procedure. The chip package was cleaned with an alkali or acid solution followed by Zn displacement (zincating)in a displacement solution which comprises NaOH, Z.sub.n o, potassium sodium tartrate and sodium nitrate. After zinc displacement the chip package was performed the electroless Ni--Cu--P deposit in the strong reducing solution which contains NaH.sub.2 PO.sub.2. The chip package deposited with Ni--Cu--P was then dipped into an organic solution as flux which is a mixture of the stearic acid and glutamic acid. Finally, dip soldering of the Ni--Cu--P deposited chip packages in a molten solder bath at a temperature 40.degree..about.80.degree. C. higher than the melting point of the corresponding Pb--Sn alloy.

Abstract: The present method for producing a barrier layer and a solder bump on a chip includes: a) providing a silicon chip with a bump base; b) forming a metal pad, e.g. an aluminum pad, on the bump base; c) having the metal pad contact with a solution containing about 120.about.150 g/l NaOH, 20.about.25 g/l ZnO, 1 g/l NaNO.sub.3 and 45.about.55 g/l C.sub.4 H.sub.4 KNaO.sub.6 .multidot.4H.sub.2 O to form thereon a zinc layer, and preferably further containing tartaric acid for reducing a dissolving rate of the metal pad.; d) having the zinc layer contact with a deposition solution to deposit thereon an electroless barrier layer, e.g. an electroless Ni-P layer; and e) dipping the resulting silicon chip into a molten solder bath to form a solder bump on the electroless barrier layer. The present invention is a simple process for manufacturing an electroless Ni-P and a solder bump on a chip.

Abstract: A process for manufacturing an iridium and palladium oxides-coated titanium electrode comprises preparing a titanium substrate having a surface, applying iridium and palladium to be formed on the surface of the titanium substrate, and heat-treating the iridium and palladium oxides-applied titanium substrate to obtain an iridium and palladium oxides-coated titanium electrode. This invention provides a process for obtaining a coated titanium electrode having therein a good adhesion between the coating material and the titanium electrode, and having an excellent electrochemical stability and a superior catalytic activity in an acidic environment.