Abstract: An input sensing unit including a plurality of first electrodes, each of which including a plurality of first main patterns and a plurality of connection patterns disposed between the first main patterns to connect two first main patterns adjacent to each other, a plurality of second electrodes each of which including a plurality of second main patterns and a plurality of connection patterns disposed between the second main patterns to connect two second main patterns adjacent to each other, and a plurality of third electrodes receiving an electrical signal that is different from that received by the second electrode. Each of the third electrodes includes a plurality of third main patterns spaced apart from the second sensing patterns in a plan view and a plurality of third connection patterns disposed between the third main patterns to connect two third main patterns adjacent to each other and spaced apart from the first connection patterns in a plan view.

Abstract: The present invention relates to a method for preparing a single isomer of 1-(1-(2-benzylphenoxy)propan-2-yl)-2-methylpiperidine in high purity.

Abstract: Proposed is an air gap adjustment apparatus. The apparatus is for enabling an air gap between the inner surface of a stator and the outer surface of a rotor, which are installed in an inner space of a housing, to be uniform overall. A plurality of fastening holes are formed so as to surround a shaft through hole of an end plate constituting the housing. A fastener, which has passed through a bearing housing of a bearing, is fastened to each fastening hole so as to mount the bearing to the end plate. An adjusting member body of an adjusting member, which has passed through the bearing housing, is positioned in an adjusting member seating part which is formed at the entrance of each fastening hole. The adjusting member rotates about the adjusting member body so that a head part may adjust the position of the bearing.

Abstract: A memory device having a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to a target voltage.

Abstract: The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

Abstract: A delay locked loop circuit is disclosed.

Abstract: A memory device having a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to a target voltage.

Abstract: The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

Abstract: The present invention discloses a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to an target voltage, and a memory device having the same.