Abstract: A switching point detection circuit for detecting a switching point according to a fabrication condition of a MOS transistor includes a reference voltage generation circuit for generating a reference voltage, a first CMOS inverter circuit for receiving the reference voltage, and a second CMOS inverter circuit for receiving the reference voltage, wherein an NMOS transistor is a dominant transistor for the reference voltage in the first CMOS inverter circuit and a PMOS transistor is a dominant transistor for the reference voltage in the second CMOS inverter circuit.

Abstract: The present invention relates to a disposable tissue structure which includes an upper unit having a plurality of compressed tissue storing units, each compressed tissue storing unit having a lower opened side and an upper closed side and being hollow and upwardly protruded from an upper surface of the upper unit for storing a compressed tissue therein which is compressed using a non-woven fabric, pulp or the like and is formed in a certain shape, so that the compressed tissue is changed to a disposable wet tissue when a certain liquid is absorbed to the compressed tissue, a middle unit which is sealingly adhered to a lower surface of the upper unit and has a certain thickness and tearing strength, the middle unit being forked in a flat plate shape, and a lower unit which is sealingly adhered to a lower surface of the middle unit and has a plurality of liquid storing units which are formed in the same construction as the inverted upper unit, the liquid storing unit having an opened upper side and closed lower

Abstract: A semiconductor device includes a clock buffer block for receiving and buffering an external clock signal and then outputting an internal clock in response is a second control signal; a clock enable buffer block, which is enabled by a buffer enable signal, for comparing a reference voltage having a constant potential with a clock enable buffer signal and then generating a first control signal; a clock enable signal timing control block for outputting the second control signal by passing the clock enable signal to the clock buffer block in response to the buffer enable signal or by delaying the clock enable signal for a predetermined time; and a clock enable signal latch block for generating the enable signal after a power-up signal is inputted.

Abstract: The present invention is a high-voltage generation circuit configured to sequentially activate a plurality of high-voltage pump circuits to precisely pump a level of high voltage. In one embodiment, the high-voltage generation circuit includes a high-voltage level detection unit for outputting a high-voltage detected signal, a high-voltage pump control unit for generating a control signal responsive to a detected signal, an oscillator for generating a pulse signal for driving a plurality of high-voltage pumps, a sequential delay unit for sequentially delaying the pulse signal from the oscillator, and a plurality of high-voltage pumps for pumping the high voltage based on a delayed pulse signal and the control signal.

Abstract: The present invention relates to a semiconductor device and, more particularly, to a clock enable buffer to output a clock enable signal which enables a clock buffer to produce an internal clock signal. The semiconductor device according to the present invention comprises: a clock buffer for receiving and buffering an external clock signal and then outputting an internal clock; a clock enable buffer for comparing a reference voltage having a constant potential with a clock enable buffer signal and then enabling the clock buffer; and a clock enable signal latch circuit for enabling the clock enable buffer using the clock enable buffer signal after a power-up signal is inputted.

Abstract: A switching point detection circuit for detecting a switching point according to a fabrication condition of MOS transistor, includes a reference voltage generation unit for generating a reference voltage, a first CMOS inverter, in which an NMOS transistor is dominant for the reference voltage, receiving the reference voltage and a second CMOS inverter, in which a PMOS transistor is dominant for the reference voltage, receiving the reference voltage.

Abstract: A buffering circuit of a semiconductor memory device is provided with a plurality of buffers divided into groups, comprising: a first controller for generating a first enable signal in response to a refresh signal and a clock enable signal; a second controller for generating a second enable signal in response to an auto-refresh signal and the first enable signal; a first buffer block including at least one of signal input buffers controlled by the first enable signal; and a second buffer block including at least one of signal input buffers controlled by the second enable signal. The groups of the buffers are independently assigned to their corresponding enable signals.

Abstract: The present invention is a high-voltage generation circuit configured to sequentially activate a plurality of high-voltage pump circuits to precisely pump a level of high voltage. In one embodiment, the high-voltage generation circuit includes a high-voltage level detection unit for outputting a high-voltage detected signal, a high-voltage pump control unit for generating a control signal responsive to a detected signal, an oscillator for generating a pulse signal for driving a plurality of high-voltage pumps, a sequential delay unit for sequentially delaying the pulse signal from the oscillator, and a plurality of high-voltage pumps for pumping the high voltage based on a delayed pulse signal and the control signal.

Abstract: A buffering circuit of a semiconductor memory device is provided with a plurality of buffers divided into groups, comprising: a first controller for generating a first enable signal in response to a refresh signal and a clock enable signal; a second controller for generating a second enable signal in response to an auto-refresh signal and the first enable signal; a first buffer block including at least one of signal input buffers controlled by the first enable signal; and a second buffer block including at least one of signal input buffers controlled by the second enable signal. The groups of the buffers are independently assigned to their corresponding enable signals.

Abstract: A self refresh controlling apparatus for use in a semiconductor memory device includes a delay unit for delaying the clock buffer enable control signal by a predetermined time and an internal clock signal activation controller for controlling activation of the internal clock signal by logically combining the internal clock signal with a control signal generated under control of the delayed clock buffer enable control signal from the delaying unit and the internal clock signal in order to prevent mis-operation due to the internal clock signal generated late in completion of self refresh operation.

Abstract: A self refresh controlling apparatus for use in a semiconductor memory device includes a delay unit for delaying the clock buffer enable control signal by a predetermined time and an internal clock signal activation controller for controlling activation of the internal clock signal by logically combining the internal clock signal with a control signal generated under control of the delayed clock buffer enable control signal from the delaying unit and the internal clock signal in order to prevent mis-operation due to the internal clock signal generated late in completion of self refresh operation.