Abstract: A memory system and an operating method thereof are provided. The memory system includes a storage device including a mode register suitable for activating or inactivating an auto mode and a memory suitable for storing data, and a storage device controller controlling the mode register to enter a test mode, after inactivating the auto mode, during a test operation of the storage device, and controlling the mode register to activate the auto mode again when the test operation of the storage device is completed.

Abstract: A memory system and an operating method thereof are provided. The memory system includes a storage device including a mode register suitable for activating or inactivating an auto mode and a memory suitable for storing data, and a storage device controller controlling the mode register to enter a test mode, after inactivating the auto mode, during a test operation of the storage device, and controlling the mode register to activate the auto mode again when the test operation of the storage device is completed.

Abstract: A memory system and an operating method thereof are provided. The memory system includes a storage device including a mode register suitable for activating or inactivating an auto mode and a memory suitable for storing data, and a storage device controller controlling the mode register to enter a test mode, after inactivating the auto mode, during a test operation of the storage device, and controlling the mode register to activate the auto mode again when the test operation of the storage device is completed.

Abstract: A memory system and an operating method thereof are provided. The memory system includes a storage device including a mode register suitable for activating or inactivating an auto mode and a memory suitable for storing data, and a storage device controller controlling the mode register to enter a test mode, after inactivating the auto mode, during a test operation of the storage device, and controlling the mode register to activate the auto mode again when the test operation of the storage device is completed.

Abstract: A data storage device includes a filter, a central processing unit (CPU), a first memory configured to store a page, a second memory, and a page type analyzer configured to analyze a type of the page output from the first memory and to transmit an indication signal to the CPU according to an analysis result. According to control of the CPU that operates based on the indication signal, the filter passes the page to the second memory or filters each row in the page, and transmits first filtered data to the second memory.

Abstract: A cache memory device is provided. The cache memory device includes a memory including a first cache memory region and a second cache memory region, and a control block. The control block determines a type of data to be received. The control block also performs at least one of transmitting a head of received data to a first cache memory region, transmitting a body of the received data to a second cache memory region and transmitting a tail of the received data to the first cache memory region based on the type of the data to be received.

Abstract: A cache memory device is provided. The cache memory device includes a memory including a first cache memory region and a second cache memory region, and a control block. The control block determines a type of data to be received. The control block also performs at least one of transmitting a head of received data to a first cache memory region, transmitting a body of the received data to a second cache memory region and transmitting a tail of the received data to the first cache memory region based on the type of the data to be received.

Abstract: A cache memory device is provided. The cache memory device includes a memory including a first cache memory region and a second cache memory region, and a control block. The control block determines a type of data to be received. The control block also performs at least one of transmitting a head of received data to a first cache memory region, transmitting a body of the received data to a second cache memory region and transmitting a tail of the received data to the first cache memory region based on the type of the data to be received.

Abstract: A data storage device includes a filter, a central processing unit (CPU), a first memory configured to store a page, a second memory, and a page type analyzer configured to analyze a type of the page output from the first memory and to transmit an indication signal to the CPU according to an analysis result. According to control of the CPU that operates based on the indication signal, the filter passes the page to the second memory or filters each row in the page, and transmits first filtered data to the second memory.

Abstract: A cache memory device is provided. The cache memory device includes a memory including a first cache memory region and a second cache memory region, and a control block. The control block determines a type of data to be received. The control block also performs at least one of transmitting a head of received data to a first cache memory region, transmitting a body of the received data to a second cache memory region and transmitting a tail of the received data to the first cache memory region based on the type of the data to be received.

Abstract: A computing system includes a host, a data source device, and a controller. The controller is configured to respond to a random access command from the host by setting information in a register that selects what data is to be accessed in the data source device. The controller then successively accesses the data in the data source device using the information that was set in the register.

Abstract: An Error Correcting Code (ECC) control circuit in a memory controller includes an ECC controller configured to receive data from a memory device in response to a request from a host device. The ECC controller transmits the data to a direct memory access (DMA) buffer for transfer to the host device, and to an ECC block for error detection and correction of the data. The ECC controller is configured to interrupt transmission of the data to the DMA buffer and transmit error-corrected data output from the ECC block to the DMA buffer responsive to detection of an error in the data by the ECC block. Related systems and methods are also discussed.

Abstract: A computing system includes a host, a data source device, and a controller. The controller is configured to respond to a random access command from the host by setting information in a register that selects what data is to be accessed in the data source device. The controller then successively accesses the data in the data source device using the information that was set in the register.

Abstract: An Error Correcting Code (ECC) control circuit in a memory controller includes an ECC controller configured to receive data from a memory device in response to a request from a host device. The ECC controller transmits the data to a direct memory access (DMA) buffer for transfer to the host device, and to an ECC block for error detection and correction of the data. The ECC controller is configured to interrupt transmission of the data to the DMA buffer and transmit error-corrected data output from the ECC block to the DMA buffer responsive to detection of an error in the data by the ECC block. Related systems and methods are also discussed.

Abstract: A cache memory device is provided. The cache memory device includes a memory including a first cache memory region and a second cache memory region, and a control block. The control block determines a type of data to be received. The control block also performs at least one of transmitting a head of received data to a first cache memory region, transmitting a body of the received data to a second cache memory region and transmitting a tail of the received data to the first cache memory region based on the type of the data to be received.

Abstract: A flash memory device includes a flash memory, a buffer memory and a control unit. The buffer memory temporarily stores data that is to be stored in the flash memory or data that is read from the flash memory. The control unit includes a buffer controller. The buffer controller performs a jump operation for transferring data unnecessary to be updated in the flash memory to an adjacent position of update data in the buffer memory when a size of data necessary to be updated in the flash memory is smaller than a size of a block of the flash memory. Therefore, the flash memory device and a flash memory system including the flash memory device may simplify an update operation with a DMA operation and a performance of a system is enhanced.