Abstract: A receptacle connector having a stable contact point structure and a rigid structure, and a connector assembly including the same, is provided. The receptacle connector includes a receptacle housing, a plurality of receptacle terminals which are retained and supported in the receptacle housing in a first direction, and one pair of receptacle metal members which are provided on both ends of the receptacle housing in the first direction.

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Abstract: A lateral power integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other in a first direction, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region arranged between the source region and the drift region in the first direction, a plurality of planar insulation field plates disposed over the drift region and spaced apart from each other in a second direction, a plurality of trench insulation field plates disposed in the drift region, a gate insulation layer formed over the channel region, and a gate electrode formed over the gate insulation layer. Each of the trench insulation field plates is disposed between the planar insulation field plates in the second direction.

Abstract: A lateral power integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other in a first direction, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region arranged between the source region and the drift region in the first direction, a plurality of planar insulation field plates disposed over the drift region and spaced apart from each other in a second direction, a plurality of trench insulation field plates disposed in the drift region, a gate insulation layer formed over the channel region, and a gate electrode formed over the gate insulation layer. Each of the trench insulation field plates is disposed between the planar insulation field plates in the second direction.

Abstract: A power integrated device includes a gate electrode on a substrate, a source region and a drain region disposed in the substrate at two opposite sides of the gate electrode, a drift region disposed in the substrate between the gate electrode and the drain region to be spaced apart from the source region, and a plurality of insulating stripes disposed in an upper region of the drift region to define at least one active stripe therebetween. Related electronic devices and related electronic systems are also provided.

Abstract: A semiconductor device includes a plurality of epitaxial layers stacked over a supportive substrate, a first buried impurity region formed to share the supportive substrate with a lowermost epitaxial layer among the multiple epitaxial layers, one or more second buried impurity regions formed to be coupled with the first buried impurity region and share an Nth epitaxial layer and an (N+1)th epitaxial layer among the multiple epitaxial layers, where N is a natural number, a body region formed in an uppermost epitaxial layer among the multiple epitaxial layers and a deep well formed in the uppermost epitaxial layer to surround the body region and to be coupled with the second buried impurity regions that share the uppermost epitaxial layer.

Abstract: A power integrated device includes a gate electrode on a substrate, a source region and a drain region disposed in the substrate at two opposite sides of the gate electrode, a drift region disposed in the substrate between the gate electrode and the drain region to be spaced apart from the source region, and a plurality of insulating stripes disposed in an upper region of the drift region to define at least one active stripe therebetween. Related electronic devices and related electronic systems are also provided.

Abstract: A semiconductor device includes a plurality of epitaxial layers stacked over a supportive substrate, a first buried impurity region formed to share the supportive substrate with a lowermost epitaxial layer among the multiple epitaxial layers, one or more second buried impurity regions formed to be coupled with the first buried impurity region and share an Nth epitaxial layer and an (N+1)th epitaxial layer among the multiple epitaxial layers, where N is a natural number, a body region formed in an uppermost epitaxial layer among the multiple epitaxial layers and a deep well formed in the uppermost epitaxial layer to surround the body region and to be coupled with the second buried impurity regions that share the uppermost epitaxial layer.

Abstract: A semiconductor device includes a plurality of epitaxial layers stacked over a supportive substrate, a first buried impurity region formed to share the supportive substrate with a lowermost epitaxial layer among the multiple epitaxial layers, one or more second buried impurity regions formed to be coupled with the first buried impurity region and share an Nth epitaxial layer and an (N+1)th epitaxial layer among the multiple epitaxial layers, where N is a natural number, a body region formed in an uppermost epitaxial layer among the multiple epitaxial layers and a deep well formed in the uppermost epitaxial layer to surround the body region and to be coupled with the second buried impurity regions that share the uppermost epitaxial layer.

Abstract: A semiconductor device includes a plurality of epitaxial layers stacked over a supportive substrate, a first buried impurity region formed to share the supportive substrate with a lowermost epitaxial layer among the multiple epitaxial layers, one or more second buried impurity regions formed to be coupled with the first buried impurity region and share an Nth epitaxial layer and an (N+1)th epitaxial layer among the multiple epitaxial layers, where N is a natural number, a body region formed in an uppermost epitaxial layer among the multiple epitaxial layers and a deep well formed in the uppermost epitaxial layer to surround the body region and to be coupled with the second buried impurity regions that share the uppermost epitaxial layer.