Abstract: A memory such as a volatile memory device capable of having a reduced area is provided. The volatile memory device comprises a first sense amplifier, a second sense amplifier spaced apart from the first sense amplifier, a first normal mat disposed between the first sense amplifier and the second sense amplifier, and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier, and a first reference mat disposed on the first normal mat between the first sense amplifier and the second sense amplifier, and including a first complementary bit line connected to the first sense amplifier and a second complementary bit line connected to the second sense amplifier.

Abstract: A volatile memory device may include; a first sense amplifier, a second sense amplifier spaced apart from the first sense amplifier in a first direction, a first mat disposed between the first sense amplifier and the second sense amplifier and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier, a third sense amplifier spaced apart from the second sense amplifier in a second direction, a fourth sense amplifier spaced apart from the third sense amplifier in the first direction, and a second mat disposed between the third sense amplifier and the fourth sense amplifier and including a first complementary bit line connected to the first sense amplifier.

Abstract: A volatile memory device having a reduced area may include; a row decoder extending in a first direction, a column decoder extending in a second direction, a cell region between the row decoder and the column decoder and including a first sense amplifier and a first bit line connected to the first sense amplifier, and a first peripheral circuit region spaced apart from the cell region in the first direction and including includes a first complementary bit line connected to the first sense amplifier. The first sense amplifier may be configured to perform a read/write operation in relation to a first memory cell connected to the first bit line using the first complementary bit line.

Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The refresh circuit is configured to: perform a second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation, and not perform the second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation. Whether the refresh control circuit performs or does not perform the second burst refresh operation is based on a comparison between an entering time for the self refresh operation of the memory cell rows and a reference time.

Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Abstract: A semiconductor memory device having a status register read function includes a plurality of data output pads electrically connected to corresponding package pin, and a swap controller connected between the plurality of data output pads and a plurality of output lines that output memory-related unique information in a specific operation mode. The swap controller controls a swap according to preset swap program information when a swap is needed to match the data output pads to the package pins.

Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Abstract: A semiconductor memory device having a status register read function includes a plurality of data output pads electrically connected to corresponding package pin, and a swap controller connected between the plurality of data output pads and a plurality of output lines that output memory-related unique information in a specific operation mode. The swap controller controls a swap according to preset swap program information when a swap is needed to match the data output pads to the package pins.

Abstract: Provided are a semiconductor integrated circuit (IC) including a pad for a wafer test and a method of testing a wafer including a semiconductor IC. The semiconductor IC includes a first address generator, a second address generator, and an address output unit. The first address generator generates a normal address having (M+N) bits or a first test address having M bits corresponding to voltages applied to a plurality of address pads. The second address generator generates a second test address having N bits corresponding to a voltage applied to an additional pad. Therefore, according to the semiconductor IC and the wafer test method, an additional pad is provided to generate an N-bit test address in wafer test mode such that the number of pads needed to test a device can be reduced. As a result, more semiconductor ICs can be tested simultaneously.

Abstract: In the semiconductor integrated circuit, an apparatus for detecting a logic state represented by an input signal includes a reference signal generating circuit and a determining circuit. The reference signal generating circuit generates a reference voltage based on a previously received input signal voltage, and the determining circuit determines a logic state represented by a currently received input signal voltage based on the reference voltage.

Abstract: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Abstract: Provided are a semiconductor integrated circuit (IC) including a pad for a wafer test and a method of testing a wafer including a semiconductor IC. The semiconductor IC includes a first address generator, a second address generator, and an address output unit. The first address generator generates a normal address having (M+N) bits or a first test address having M bits corresponding to voltages applied to a plurality of address pads. The second address generator generates a second test address having N bits corresponding to a voltage applied to an additional pad. Therefore, according to the semiconductor IC and the wafer test method, an additional pad is provided to generate an N-bit test address in wafer test mode such that the number of pads needed to test a device can be reduced. As a result, more semiconductor ICs can be tested simultaneously.

Abstract: A semiconductor device includes a memory and a power voltage interrupter configured to interrupt an external power voltage applied to circuitry of the semiconductor device responsive to a Deep Power Down (DPD) command signal generated in a DPD mode of the memory. A power voltage shifter is configured to shift a power voltage in the circuitry to a specific level responsive to the DPD command signal.

Abstract: A semiconductor device includes a memory and a power voltage interrupter configured to interrupt an external power voltage applied to circuitry of the semiconductor device responsive to a Deep Power Down (DPD) command signal generated in a DPD mode of the memory. A power voltage shifter is configured to shift a power voltage in the circuitry to a specific level responsive to the DPD command signal.

Abstract: Provided are an integrated circuit and a method thereof, in which different types of signals can be applied to an internal circuit via one pin. The integrated circuit device includes a distribution unit, a level fixing unit, and an activation unit. The distribution unit receives and outputs a first input signal input via the first input pin, and receives and outputs a second input signal input via the first input pin in response to a control signal. The level fixing unit receives the first input signal from the distribution unit and applies a signal having the same voltage level as the first input signal to a first internal circuit in response to the control signal. The activation unit receives the second input signal input via the second input pin and then applies the second input signal to a second internal circuit or applies the second input signal output from the distribution unit to the second internal circuit in response to the control signal.