Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.

Abstract: A semiconductor system includes a controller configured to count the number of error check scrub (ECS) operations and configured to generate ECS information that includes information with regard to an address at which the ECS operation is to be performed based on the number of ECS operations. The semiconductor system further includes a memory apparatus configured to perform the ECS operation on a region that is selected by the ECS information.

Abstract: A data output control circuit includes a dividing circuit, a timing signal generating circuit and a control signal generating circuit. The dividing circuit divides read enable signals to generate multiple phase clock signals. The timing signal generating circuit generates a plurality of timing signals based on warming-up cycle information and the multiple phase clock signals. The control signal generating circuit generates data output control signals based on the multiple phase clock signals and the plurality of timing signals.

Abstract: A memory device includes an auto error check scrub (ECS) control circuit configured to generate an auto ECS command for performing an ECS operation based on a refresh control signal. The memory device also includes a burst ECS control circuit configured to generate an internal burst ECS command for performing the ECS operation every set period based on a burst ECS command and an ECS end flag. The memory device further includes an ECS address generation circuit configured to generate an ECS address for the ECS operation by counting an input of the auto ECS command or the internal burst ECS command and to generate the ECS end flag based on a value of the ECS address.

Abstract: An electronic device includes a pre-charge control circuit configured to generate first and second pre-charge signals with pulses that are selectively generated based on a first and second output control signals that are generated during a read operation, and a data processing circuit configured to pre-charge one of first and second internal nodes based on the first and second pre-charge signals, latch internal data based on first and second input control signals, and output data that is generated from the latched internal data to an external device based on the first and second output control signals. The data is generated from the internal data that is transmitted through one of the first and second internal nodes.

Abstract: A pipe latch circuit includes a data latch circuit configured to latch an input data based on an input control signal and output the latched input data as a latch data based on an output control signal, a sense amplification circuit configured to sense and amplify the latch data based on a sum output control signal, and a data driving circuit configured to drive an output data from the latch data based on the sum output control signal.

Abstract: A memory device includes an auto error check scrub (ECS) control circuit configured to generate an auto ECS command for performing an ECS operation based on a refresh control signal. The memory device also includes a burst ECS control circuit configured to generate an internal burst ECS command for performing the ECS operation every set period based on a burst ECS command and an ECS end flag. The memory device further includes an ECS address generation circuit configured to generate an ECS address for the ECS operation by counting an input of the auto ECS command or the internal burst ECS command and to generate the ECS end flag based on a value of the ECS address.

Abstract: The present disclosure relates to a synthetic vegetable oil and an environmental-friendly flame-retardant hydraulic oil composition including the same, and a preparation method thereof, and provides a method of preparing a glycerin-ester-based lubricating base oil through a catalyst-free and rinsing-free process, a glycerin-ester-based lubricating base oil that is a synthetic vegetable oil obtained by the method, and an environmental-friendly flame-retardant hydraulic oil composition that contains the glycerin-ester-based lubricating base oil and that is capable of reducing electricity consumption by 7 to 8% compared to mineral oil-based lubricating oils due to excellent flame retardancy (with self-extinguishing function) and lubricity.

Abstract: A semiconductor device includes: a memory cell array including a plurality of memory cells; a data input/output circuit suitable for outputting data provided from the memory cell array in response to a couple of data output control signals; and a data output control circuit suitable for generating a couple of latch read enable signals and a couple of data output control timing signals based on a couple of complementary read enable signals, an internal enable signal and warming-up cycle information indicating different warming-up cycles, and outputting, according to the couple of data output control timing signals, the couple of data output control signals using the couple of latch read enable signals, one or more pulses of each of which are masked according to the warming-up cycle information.

Abstract: A data output control circuit includes a dividing circuit, a timing signal generating circuit and a control signal generating circuit. The dividing circuit divides read enable signals to generate multiple phase clock signals. The timing signal generating circuit generates a plurality of timing signals based on warming-up cycle information and the multiple phase clock signals. The control signal generating circuit generates data output control signals based on the multiple phase clock signals and the plurality of timing signals.

Abstract: A semiconductor device includes a sampling code generation circuit and a code comparator. The sampling code generation circuit includes a buffer circuit configured to receive an external set signal. The sampling code generation circuit is configured to perform a count operation during a sampling period, the sampling period adjusted based on an output signal of the buffer circuit to generate a sampling code. The code comparator is configured to compare the sampling code with a reference code to generate a comparison flag.

Abstract: A pipe latch circuit includes a data latch circuit configured to latch an input data based on an input control signal and output the latched input data as a latch data based on an output control signal, a sense amplification circuit configured to sense and amplify the latch data based on a sum output control signal, and a data driving circuit configured to drive an output data from the latch data based on the sum output control signal.

Abstract: An apparatus includes a control clock generation circuit configured to generate a first toggling reference clock from a first internal clock and generate a second toggling reference clock from a first inverted internal clock, when a read operation is performed. The apparatus also includes a strobe signal generation circuit configured to generate a data strobe signal whose level transitions during a toggling period in synchronization with the first and second toggling reference clocks.

Abstract: An apparatus includes a control dock generation circuit configured to generate a first toggling reference dock from a first internal dock and generate a second toggling reference dock from a first inverted internal dock, when a read operation is performed. The apparatus also includes a strobe signal generation circuit configured to generate a data strobe signal whose level transitions during a toggling period in synchronization with the first and second toggling reference docks.

Abstract: An electronic device includes a pre-charge control circuit configured to generate first and second pre-charge signals with pulses that are selectively generated based on a first and second output control signals that are generated during a read operation, and a data processing circuit configured to pre-charge one of first and second internal nodes based on the first and second pre-charge signals, latch internal data based on first and second input control signals, and output data that is generated from the latched internal data to an external device based on the first and second output control signals. The data is generated from the internal data that is transmitted through one of the first and second internal nodes.

Abstract: A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the reset control signal and generates first and third divided clock signals.

Abstract: A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the reset control signal and generates first and third divided clock signals.

Abstract: The present disclosure relates to a synthetic vegetable oil and an environmental-friendly flame-retardant hydraulic oil composition including the same, and a preparation method thereof, and provides a method of preparing a glycerin-ester-based lubricating base oil through a catalyst-free and rinsing-free process, a glycerin-ester-based lubricating base oil that is a synthetic vegetable oil obtained by the method, and an environmental-friendly flame-retardant hydraulic oil composition that contains the glycerin-ester-based lubricating base oil and that is capable of reducing electricity consumption by 7 to 8% compared to mineral oil-based lubricating oils due to excellent flame retardancy (with self-extinguishing function) and lubricity.

Abstract: A scheduling method for grant-free multiple access, and a user terminal for the same are disclosed. The method comprises: (a) a step of receiving, from the user terminal, information on traffic to be served, network information of the user terminal and state information of the user terminal; (b) a scheduling step of forming scheduling groups on the basis of the information received in step (a) and a step of allocating resources to each scheduling group; and (c) providing scheduling information to the user terminal, wherein traffic aggregations for traffic of the terminal are set on the basis of the information on traffic from the terminal, the scheduling groups are formed according to the traffic aggregations, and the scheduling information is provided to each traffic aggregation by which the user terminal is to be served.

Abstract: A semiconductor device includes a sampling code generation circuit and a code comparator. The sampling code generation circuit includes a buffer circuit configured to receive an external set signal. The sampling code generation circuit is configured to perform a count operation during a sampling period, the sampling period adjusted based on an output signal of the buffer circuit to generate a sampling code. The code comparator is configured to compare the sampling code with a reference code to generate a comparison flag.