Patents by Inventor Kwang Su Choe

Kwang Su Choe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136674
    Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on a winding axis to define a core and an outer circumference. The first electrode includes a first active material portion coated with an active material layer and a first uncoated portion not coated with an active material layer along a winding direction. At least a part of the first uncoated portion is defined as an electrode tab by itself. The first uncoated portion includes a first portion adjacent to the core of the electrode assembly, a second portion adjacent to the outer circumference of the electrode assembly, and a third portion interposed between the first portion and the second portion. The first portion or the second portion has a smaller height than the third portion in the winding axis direction.
    Type: Application
    Filed: January 19, 2022
    Publication date: April 25, 2024
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Jong-Sik PARK, Jae-Won LIM, Yu-Sung CHOE, Hak-Kyun KIM, Je-Jun LEE, Byoung-Gu LEE, Duk-Hyun RYU, Kwan-Hee LEE, Jae-Eun LEE, Pil-Kyu PARK, Kwang-Su HWANGBO, Do-Gyun KIM, Geon-Woo MIN, Hae-Jin LIM, Min-Ki JO, Su-Ji CHOI, Bo-Hyun KANG, Jae-Woong KIM, Ji-Min JUNG, Jin-Hak KONG, Soon-O LEE, Kyu-Hyun CHOI
  • Patent number: 7718231
    Abstract: A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: May 18, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kwang Su Choe, Keith E. Fogel, Siegfried L. Maurer, Ryan M. Mitchell, Devendra K. Sadana
  • Patent number: 7566482
    Abstract: A method in which a SOI substrate structure is fabricated by oxidation of graded porous Si is provided. The graded porous Si is formed by first implanting a dopant (p- or n-type) into a Si-containing substrate, activating the dopant using an activation anneal step and then anodizing the implanted and activated dopant region in a HF-containing solution. The graded porous Si has a relatively coarse top layer and a fine porous layer that is buried beneath the top layer. Upon a subsequent oxidation step, the fine buried porous layer is converted into a buried oxide, while the coarse top layer coalesces into a solid Si-containing over-layer by surface migration of Si atoms.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: July 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Kwang Su Choe, Keith E. Fogel, Devendra K. Sadana
  • Patent number: 7125458
    Abstract: A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: October 24, 2006
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Kwang Su Choe, Keith E. Fogel, Devendra K. Sadana
  • Patent number: 6878611
    Abstract: In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.
    Type: Grant
    Filed: January 2, 2003
    Date of Patent: April 12, 2005
    Assignee: International Business Machines Corporation
    Inventors: Devendra K. Sadana, Stephen W. Bedell, Tze-Chiang Chen, Kwang Su Choe, Keith E. Fogel
  • Patent number: 6800518
    Abstract: A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structure are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: October 5, 2004
    Assignee: International Business Machines Corporation
    Inventors: Robert E. Bendernagel, Kwang Su Choe, Bijan Davari, Keith E. Fogel, Devendra K. Sadana, Ghavam G. Shahidi, Sandip Tiwari
  • Publication number: 20040132267
    Abstract: In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.
    Type: Application
    Filed: January 2, 2003
    Publication date: July 8, 2004
    Applicant: International Business Machines Corporation
    Inventors: Devendra K. Sadana, Stephen W. Bedell, Tze-Chiang Chen, Kwang Su Choe, Keith E Fogel
  • Publication number: 20040126985
    Abstract: A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structures are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 1, 2004
    Inventors: Robert E. Bendernagel, Kwang Su Choe, Bijan Davari, Keith E. Fogel, Devendra K. Sadana, Ghavam G. Shahidi, Sandip Tiwari