Abstract: A secondary battery includes: an electrode assembly including a first electrode plate from which a first current collecting tab protrudes, a second electrode plate from which a second current collecting tab protrudes, and a separator between the first electrode plate and the second electrode plate; a case accommodating the electrode assembly; and a current collector plate electrically connected to the first current collecting tab and including protrusions, and the first current collecting tab is vertically coupled to the current collector plate and includes coupling grooves to which the protrusions are coupled.

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Abstract: An orthodontic wire bending device includes a providing part, a bending unit and a cutting part. The providing part is configured to provide a wire. The bending unit is disposed at a front side of the providing part, and includes a fixing part and a bending part. The fixing part is configured to fix the wire. The bending part is configured to bend the wire fixed by the fixing part. The cutting part is configured to cut the wire bent by the bending part. The bending part includes a bending module, and the bending module is rotated along a circumferential direction or moves along a direction to make contact with at least one side of the wire for bending the wire.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: A display includes a plurality of pixels in a non-quadrangular display area and a plurality of first driving circuits and a plurality of second driving circuits in a peripheral area of the display area. Each of the pixels is connected to a first signal line in a first direction and a second signal line in a second direction crossing the first direction. Each of the first driving circuits outputs a first signal to the first signal line of a corresponding one of the pixels. Each of the second driving circuits outputs a second signal to the second signal line of a corresponding one of the pixels. The number of second driving circuits between neighboring first driving circuits is different depending on a position in the peripheral area.

Abstract: The present invention relates to a pidolate salt and malate salt of a compound represented by a formula 1 with an excellent liquid-phase stability, solid-phase stability, water solubility, precipitation stability and hygroscopicity all together as a compound for preventing and treating diseases mediated by an acid pump antagonistic activity, as well as a method for preparing the same.

Abstract: A method for translating memory addresses in a manycore system is provided, which is executed by one or more processors, and includes receiving identification information of a thread accessing a memory associated with one or more cores of a cluster that includes a plurality of cores, receiving a virtual address of data accessed by the thread, and determining a physical address of data in the memory based on the virtual address and the identification information of the thread.

Abstract: A memory controller includes a buffer memory configured to store first meta data and second meta data having a different type from the first meta data, and a cache memory including first and second dedicated areas. The first meta data is cached in the first dedicated area and the second meta data is cached in the second dedicated area.

Abstract: A controller for controlling a memory device is provided to include: a request receiver configured to receive a request including a logical address from a host; a dependency checker configured to acquire the request from the request receiver and check a dependency of the request; a map manager configured to generate a command including a physical address mapped to the logical address of the request in response to a result of checking that the request has no dependency on the prior incomplete request; and a command submitter configured to provide the memory device with the command generated by the map manager, wherein the request receiver, the dependency checker, the map manager and the command submitter are structured to configure a data pipeline such that operations of the request receiver, the dependency checker, the map manager, and the command submitter deliver are performed in series.

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may store target data to be programmed in a memory device in a first memory, selectively store the target data in a second memory, program the target data stored in the first memory into the memory device, and reprogram the target data stored in the first memory or the second memory into the memory device when the programming of the target data stored in the first memory into the memory device fails. The buffer circuit may input the target data input from the memory controller into the second memory or discard the target data.

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

Abstract: A controller for controlling a memory device is provided to include: a request receiver configured to receive a request including a logical address from a host; a dependency checker configured to acquire the request from the request receiver and check a dependency of the request; a map manager configured to generate a command including a physical address mapped to the logical address of the request in response to a result of checking that the request has no dependency on the prior incomplete request; and a command submitter configured to provide the memory device with the command generated by the map manager, wherein the request receiver, the dependency checker, the map manager and the command submitter are structured to configure a data pipeline such that operations of the request receiver, the dependency checker, the map manager, and the command submitter deliver are performed in series.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may store target data to be programmed in a memory device in a first memory, selectively store the target data in a second memory, program the target data stored in the first memory into the memory device, and reprogram the target data stored in the first memory or the second memory into the memory device when the programming of the target data stored in the first memory into the memory device fails. The buffer circuit may input the target data input from the memory controller into the second memory or discard the target data.

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

Abstract: A memory controller includes a buffer memory configured to store first meta data and second meta data having a different type from the first meta data, and a cache memory including first and second dedicated areas. The first meta data is cached in the first dedicated area and the second meta data is cached in the second dedicated area.

Abstract: A method of protecting data of a flash memory is provided. The method includes detecting primary power applied to the flash memory, and applying secondary power converted from the primary power to the flash memory. The primary power is compared to first and second values, and a writing-protection pin of the flash memory is enabled when the detected primary power reaches a predetermined value.