Patents by Inventor Kwangtae HWANG
Kwangtae HWANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11837545Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.Type: GrantFiled: August 10, 2021Date of Patent: December 5, 2023Inventors: Jungwoo Song, Ye-Ro Lee, Kwangtae Hwang, Kwangmin Kim, Yong Kwan Kim, Jiyoung Kim
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Patent number: 11450554Abstract: To manufacture an integrated circuit (IC) device, a lower structure having a step structure defining a trench is prepared. A material film is formed inside the trench. To form a material film, a first precursor including a first central element and a first ligand having a first size is supplied onto a lower structure to form a first chemisorbed layer of the first precursor on the lower structure. A second precursor including a second central element and a second ligand having a second size less than the first size is supplied onto a resultant structure including the first chemisorbed layer to form a second chemisorbed layer of the second precursor on the lower structure. A reactive gas is supplied to the first chemisorbed layer and the second chemisorbed layer.Type: GrantFiled: August 26, 2020Date of Patent: September 20, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Geumbi Mun, Jinyong Kim, Junwon Lee, Kwangtae Hwang, Iksoo Kim, Jiwoon Im
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Patent number: 11264219Abstract: Provided are a radical monitoring apparatus capable of monitoring electrical diagnosis of a radical produced by direct plasma or remote plasma and the amount of change of the produced radical, and a plasma apparatus including the radical monitoring apparatus. The plasma apparatus includes a process chamber in which a plasma process is performed, a dielectric film in the process chamber and surrounding sides of a plasma discharge space in the process chamber, and a sensor inside the dielectric film and configured to monitor plasma to thereby monitor a radical generated in the plasma.Type: GrantFiled: March 10, 2020Date of Patent: March 1, 2022Inventors: Kwangtae Hwang, Jinyong Kim, Iksoo Kim, Geumbi Mun, Junwon Lee, Jiwoon Im
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Publication number: 20210375764Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.Type: ApplicationFiled: August 10, 2021Publication date: December 2, 2021Inventors: JUNGWOO SONG, Ye-Ro LEE, Kwangtae HWANG, Kwangmin KIM, YONG KWAN KIM, JIYOUNG KIM
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Publication number: 20210193508Abstract: To manufacture an integrated circuit (IC) device, a lower structure having a step structure defining a trench is prepared. A material film is formed inside the trench. To form a material film, a first precursor including a first central element and a first ligand having a first size is supplied onto a lower structure to form a first chemisorbed layer of the first precursor on the lower structure. A second precursor including a second central element and a second ligand having a second size less than the first size is supplied onto a resultant structure including the first chemisorbed layer to form a second chemisorbed layer of the second precursor on the lower structure. A reactive gas is supplied to the first chemisorbed layer and the second chemisorbed layer.Type: ApplicationFiled: August 26, 2020Publication date: June 24, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Geumbi Mun, Jinyong Kim, Junwon Lee, Kwangtae Hwang, Iksoo Kim, Jiwoon Im
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Publication number: 20200335313Abstract: Provided are a radical monitoring apparatus capable of monitoring electrical diagnosis of a radical produced by direct plasma or remote plasma and the amount of change of the produced radical, and a plasma apparatus including the radical monitoring apparatus. The plasma apparatus includes a process chamber in which a plasma process is performed, a dielectric film in the process chamber and surrounding sides of a plasma discharge space in the process chamber, and a sensor inside the dielectric film and configured to monitor plasma to thereby monitor a radical generated in the plasma.Type: ApplicationFiled: March 10, 2020Publication date: October 22, 2020Inventors: Kwangtae Hwang, Jinyong Kim, lksoo Kim, Geumbi Mun, Junwon Lee, Jiwoon Im
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Publication number: 20200006231Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.Type: ApplicationFiled: September 4, 2019Publication date: January 2, 2020Inventors: JUNGWOO SONG, Ye-Ro LEE, Kwangtae HWANG, Kwangmin KIM, YONG KWAN KIM, JIYOUNG KIM
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Patent number: 10453796Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.Type: GrantFiled: September 15, 2017Date of Patent: October 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jungwoo Song, Ye-Ro Lee, Kwangtae Hwang, Kwangmin Kim, Yong Kwan Kim, Jiyoung Kim
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Patent number: 10347527Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.Type: GrantFiled: May 9, 2018Date of Patent: July 9, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sangho Rha, Kyoung Hee Nam, Jeonggil Lee, Hyunseok Lim, Seungjong Park, Seulgi Bae, Jaejin Lee, Kwangtae Hwang
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Publication number: 20180261499Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.Type: ApplicationFiled: May 9, 2018Publication date: September 13, 2018Inventors: SANGHO RHA, KYOUNG HEE NAM, JEONGGIL LEE, HYUNSEOK LIM, SEUNGJONG PARK, SEULGI BAE, JAEJIN LEE, KWANGTAE HWANG
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Publication number: 20180174971Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.Type: ApplicationFiled: September 15, 2017Publication date: June 21, 2018Inventors: JUNGWOO SONG, Ye-Ro LEE, Kwangtae HWANG, Kwangmin KIM, YONG KWAN KIM, JIYOUNG KIM
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Patent number: 9997400Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.Type: GrantFiled: October 24, 2016Date of Patent: June 12, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sangho Rha, Kyoung Hee Nam, Jeonggil Lee, Hyunseok Lim, Seungjong Park, Seulgi Bae, Jaejin Lee, Kwangtae Hwang
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Publication number: 20170170058Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.Type: ApplicationFiled: October 24, 2016Publication date: June 15, 2017Inventors: SANGHO RHA, KYOUNG HEE NAM, JEONGGIL LEE, HYUNSEOK LIM, SEUNGJONG PARK, SEULGI BAE, JAEJIN LEE, KWANGTAE HWANG
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Patent number: 8816418Abstract: A semiconductor memory device includes at least one supporting pattern on a substrate, a storage node penetrating the supporting pattern, an electrode layer disposed around the storage node and the supporting pattern, and a capacitor dielectric interposed between the storage node and the electrode layer. The supporting pattern includes germanium oxide.Type: GrantFiled: September 14, 2012Date of Patent: August 26, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyongsoo Kim, Eunkee Hong, Kwangtae Hwang
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Publication number: 20130105873Abstract: A semiconductor memory device includes at least one supporting pattern on a substrate, a storage node penetrating the supporting pattern, an electrode layer disposed around the storage node and the supporting pattern, and a capacitor dielectric interposed between the storage node and the electrode layer. The supporting pattern includes germanium oxide.Type: ApplicationFiled: September 14, 2012Publication date: May 2, 2013Inventors: Hyongsoo KIM, Eunkee HONG, Kwangtae HWANG