Abstract: A semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes steps of: depositing an N-drift layer on a substrate, conducting an ion implant process on the N-drift layer to form a plurality of P-type pillars, depositing a N-type epitaxial layer on the P-type pillars, conducting an ion implant process on the N-type epitaxial layer to form a first P-type epitaxial layer and at least one localized P region, conducting a field oxidation to the first P-type epitaxial layer to form a second P-type epitaxial layer, and forming a field oxide layer on the first P-type epitaxial layer and the N-type epitaxial layer. The localized P region passes though the N-type epitaxial layer to the field oxide layer.

Abstract: Provided is a super junction semiconductor device. The super junction semiconductor device includes a vertical pillar region located in an active region and horizontal pillar regions located in a termination region that are connected with each other while simultaneously not floating the entire pillar region in the termination region. Thus, a charge compensation difference, generated among pillar regions, is caused to be offset, although the length of the termination region is relatively short.

Abstract: There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a substrate, two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate, a p-type body region disposed on at least one of the p-type semiconductor regions, and a source region disposed in the p-type body region, and an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions.

Abstract: There is provided a super junction semiconductor device. The super junction semiconductor device includes a cell area and a junction termination area disposed on a substrate, and a transition area disposed between the cell area and the junction termination area, and the cell area, the junction termination area, and the transition area each include one or more unit cells comprising a N-type pillar region and a P-type pillar region among a plurality of N-type pillar regions and a P-type pillar regions that are alternated between the cell area and the junction termination area.

Abstract: There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a substrate, two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate, a p-type body region disposed on at least one of the p-type semiconductor regions, and a source region disposed in the p-type body region, and an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions.

Abstract: Provided is a super junction semiconductor device. The super junction semiconductor device includes a vertical pillar region located in an active region and horizontal pillar regions located in a termination region that are connected with each other while simultaneously not floating the entire pillar region in the termination region. Thus, a charge compensation difference, generated among pillar regions, is caused to be offset, although the length of the termination region is relatively short.

Abstract: There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a substrate, two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate, a p-type body region disposed on at least one of the p-type semiconductor regions, and a source region disposed in the p-type body region, and an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions.

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, and a super junction area that is disposed above the substrate. The super junction area may include pillars of different doping types that are alternately disposed. One of the pillars of the super junction area may have a doping concentration that gradually decreases and then increases from bottom to top in a vertical direction of the semiconductor device.

Abstract: There is provided a super junction semiconductor device. The super junction semiconductor device includes a cell area and a junction termination area disposed on a substrate, and a transition area disposed between the cell area and the junction termination area, and the cell area, the junction termination area, and the transition area each include one or more unit cells comprising a N-type pillar region and a P-type pillar region among a plurality of N-type pillar regions and a P-type pillar regions that are alternated between the cell area and the junction termination area.

Abstract: There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a substrate, two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate, a p-type body region disposed on at least one of the p-type semiconductor regions, and a source region disposed in the p-type body region, and an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions.

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, and a super junction area that is disposed above the substrate. The super junction area may include pillars of different doping types that are alternately disposed. One of the pillars of the super junction area may have a doping concentration that gradually decreases and then increases from bottom to top in a vertical direction of the semiconductor device.

Abstract: A high power semiconductor device capable of preventing parasitical bipolar transistor from turning on comprises a first conduction type drain region, a first conduction type epitaxial region formed on the first conduction type drain region, a plurality of second conduction type body regions formed on the surface of the epitaxial region, at least a first conduction type source region formed on the surface of the body regions, a source electrode contact region formed on the surface of the body regions and overlapping the source region and having at least one end longer than one end of the source region, and a plurality of gate electrodes staggered with the source electrode contact region and formed on the body regions and the epitaxial region.

Abstract: A high power semiconductor device capable of preventing parasitical bipolar transistor from turning on comprises a first conduction type drain region, a first conduction type epitaxial region formed on the first conduction type drain region, a plurality of second conduction type body regions formed on the surface of the epitaxial region, at least a first conduction type source region formed on the surface of the body regions, a source electrode contact region formed on the surface of the body regions and overlapping the source region and having at least one end longer than one end of the source region, and a plurality of gate electrodes staggered with the source electrode contact region and formed on the body regions and the epitaxial region.

Abstract: A sense FET is provided that is capable of achieving one of many available sense current ratios after manufacture, and a method of manufacturing the same. The sense FET includes a main cell array of MOSFET cells connected in parallel, and a main pad connected to the sources of the main cells. A plurality of unit sense cells are arranged in arrays, and also optionally in groups corresponding to portions of the arrays. A plurality of sense pads are electrically insulated from each other. Each sense pad is connected to the sources of the unit sense cells of either a complete sense cell array, or of a group corresponding to a portion of an array. Every sense pad is connected either to the sense resistor or to the main pad. When connected to a sense resistor, the corresponding unit cells are used as sense cells.