Abstract: A display apparatus including a display region including a first high pixel connected to a first gate line and a first data line, and a first low pixel connected to the first gate line and a second data line, the first high pixel being configured to represent a first high grayscale level, the first low pixel being configured to represent a first low grayscale level, a gate driver configured to apply a gate signal to the gate line, a data driver including a first output part configured to apply a data voltage to the first data line and the second data line, and a selecting part configured to alternately connect the first data line and the second data line to the first output part of the data driver.

Abstract: A gate driver includes first and second shift registers and a selector. The first shift register outputs first pulses. The second shift register outputs second pulses different from the first pulses. The selector selects one of the first pulses or the second pulses. When the selector selects the first pulses, the gate driver generates a first gate signal including first and second high periods, and output the first gate signal to a first gate line. The second high period is apart from the first high period by a first interval. When the selector selects the second pulses, the gate driver generates a second gate signal including the first high period and a third high period, and output the second gate signal to the first gate line. The third high period is apart from the first high period by a second interval different from the first interval.

Abstract: An exemplary embodiment provides a thin film transistor array panel, including: a substrate; an oxide semiconductor layer disposed on the substrate; an insulating layer disposed on the oxide semiconductor layer; and a pixel electrode disposed on the insulating layer. The oxide semiconductor layer includes a first layer and a second layer disposed on the first layer, the second layer includes an oxide semiconductor including silicon, and the second layer contacts the insulating layer.

Abstract: A liquid crystal display according to an exemplary embodiment of the present disclosure includes: a first substrate where a pixel electrode is formed; a second substrate facing the first substrate; a liquid crystal layer provided between the first substrate and the second substrate; and a driving device connected with the first substrate, wherein the first substrate includes a pixel area where pixels emit light, and a load storage area provided between the pixel area and the driving device and constantly maintaining a load applied to the pixels in the pixel area.

Abstract: A gate driver includes first and second shift registers and a selector. The first shift register outputs first pulses. The second shift register outputs second pulses different from the first pulses. The selector selects one of the first pulses or the second pulses. When the selector selects the first pulses, the gate driver generates a first gate signal including first and second high periods, and output the first gate signal to a first gate line. The second high period is apart from the first high period by a first interval. When the selector selects the second pulses, the gate driver generates a second gate signal including the first high period and a third high period, and output the second gate signal to the first gate line. The third high period is apart from the first high period by a second interval different from the first interval.

Abstract: A display apparatus including a display region including a first high pixel connected to a first gate line and a first data line, and a first low pixel connected to the first gate line and a second data line, the first high pixel being configured to represent a first high grayscale level, the first low pixel being configured to represent a first low grayscale level, a gate driver configured to apply a gate signal to the gate line, a data driver including a first output part configured to apply a data voltage to the first data line and the second data line, and a selecting part configured to alternately connect the first data line and the second data line to the first output part of the data driver.

Abstract: A display apparatus includes a display panel including a gate line disposed in a display area and extending in a first direction, a data line extending in a second direction crossing the first direction and a switching element electrically connected to the gate line and the data line. A first data driving part is electrically connected to a first peripheral area adjacent to the display area. A second data driving part is electrically connected to a second peripheral area adjacent to the first peripheral area. The display panel includes a voltage connecting line disposed between the first peripheral area and the second peripheral area. The voltage connecting line connects the first data driving part to the second data driving part.

Abstract: A liquid crystal display according to an exemplary embodiment of the present disclosure includes: a first substrate where a pixel electrode is formed; a second substrate facing the first substrate; a liquid crystal layer provided between the first substrate and the second substrate; and a driving device connected with the first substrate, wherein the first substrate includes a pixel area where pixels emit light, and a load storage area provided between the pixel area and the driving device and constantly maintaining a load applied to the pixels in the pixel area.

Abstract: An exemplary embodiment provides a thin film transistor array panel, including: a substrate; an oxide semiconductor layer disposed on the substrate; an insulating layer disposed on the oxide semiconductor layer; and a pixel electrode disposed on the insulating layer. The oxide semiconductor layer includes a first layer and a second layer disposed on the first layer, the second layer includes an oxide semiconductor including silicon, and the second layer contacts the insulating layer.

Abstract: A liquid crystal display includes; a liquid crystal panel, and a DC-DC converter which receives an input voltage to generate an analog drive voltage and a gate-on voltage used to operate the liquid crystal panel, wherein the DC-DC converter includes a pulse width modulation circuit which modulates a pulse width of the analog drive voltage and the gate-on voltage, a boost converter which boosts the input voltage to output the analog drive voltage, and a charge pump which boosts one of the input voltage and the analog drive voltage to output the gate-on voltage, wherein when a high voltage stress test is performed, the DC-DC converter outputs the analog drive voltage boosted to a voltage level higher than a voltage level of the analog drive voltage during a normal operation, and outputs the gate-on voltage having a voltage level substantially equal to a voltage level of the gate-on voltage during the normal operation.

Abstract: A display device and a method of driving the same are provided. The display device includes a display panel including a plurality of pixels defined in an area where a plurality of gate lines and data lines cross one another, a clock generator generating a gate clock signal using a clock generation control signal provided from a timing controller and a gate-on voltage, and a gate driver providing a gate signal to the gate lines in response to the gate clock signal. The gate signal includes a pre-charge period having a first gate-on level and a main-charge period having a second gate-on level that is higher than the first gate-on level.

Abstract: A liquid crystal display includes; a liquid crystal panel, and a DC-DC converter which receives an input voltage to generate an analog drive voltage and a gate-on voltage used to operate the liquid crystal panel, wherein the DC-DC converter includes a pulse width modulation circuit which modulates a pulse width of the analog drive voltage and the gate-on voltage, a boost converter which boosts the input voltage to output the analog drive voltage, and a charge pump which boosts one of the input voltage and the analog drive voltage to output the gate-on voltage, wherein when a high voltage stress test is performed, the DC-DC converter outputs the analog drive voltage boosted to a voltage level higher than a voltage level of the analog drive voltage during a normal operation, and outputs the gate-on voltage having a voltage level substantially equal to a voltage level of the gate-on voltage during the normal operation.