Abstract: The present invention relates to an antigen-binding molecule comprising a heavy chain variable region comprising a heavy-chain complementarity-determining region 1 (HCDR1) comprising an amino acid sequence represented by Sequence No. 1, an HCDR2 comprising an amino acid sequence represented by Sequence No. 2, and an HCDR3 comprising an amino acid sequence represented by Sequence No. 3; a light-chain variable region comprising a light-chain complementarity-determining region 1 (LCDR1) comprising an amino acid sequence represented by Sequence No. 4, an LCDR2 comprising an amino acid sequence represented by Sequence No. 5, and an LCDR3 comprising an amino acid sequence represented by Sequence No. 6; wherein the antigen-binding molecule is a T cell receptor (TCR); and to a cell line expressing the same.

Abstract: A photonic integrated circuit embedded substrate may include: an embedded insulating layer on which a photonic integrated circuit is disposed, and at least one first insulating layer stacked on one surface of the embedded insulating layer. The at least one first insulating layer may have an optical path extending in a stacking direction of the at least one first insulating layer.

Abstract: According to an embodiment, a method of simulating a three-dimensional (3D) padded garment includes generating a second pattern corresponding to a first pattern that is a two-dimensional (2D) pattern, generating an intermediate pattern positioned between the first pattern and the second pattern to which a pressure value is applied, wherein the intermediate pattern comprises a collision value, and generating the 3D padded garment based on at least one of the first pattern, the second pattern, and the intermediate pattern.

Abstract: A printed circuit board (PCB) includes a substrate including a first insulating layer and first wiring patterns disposed on the first insulating layer, an optical sensing chip including a vertical cavity surface emitting laser (VCSEL) and a photodiode, disposed on the first insulating layer to be in contact with at least one of the first wiring patterns, a transimpedance amplifier (TIA) chip disposed to be spaced apart from the optical sensing chip on the first insulating layer and disposed to be in contact with at least one first wiring pattern, different from the first wiring pattern connected to the optical sensing chip, among the first wiring patterns, and a dielectric layer stacked on the substrate and having a hole exposing the VCSEL and the photodiode of the optical sensing chip. The optical sensing chip and the transimpedance amplifier chip are connected through a wiring pattern disposed on the dielectric layer.

Abstract: The present disclosure relates to a printed circuit board and a module including the same. The printed circuit board includes an insulating body, a wiring pattern embedded in the insulating body, and a first conductor pattern disposed on the insulating body and overlapping at least a portion of the wiring pattern in a first direction. First conductive vias each penetrate a portion of the insulating body and are respectively disposed on opposite sides of the wiring pattern, in a second direction orthogonal to the first direction, to surround at least a portion of the wiring pattern. Each first conductive via has a first surface connected to the first conductor pattern, and a second surface, opposite to the first surface, connected to the insulating body.

Abstract: The present disclosure relates to a printed circuit board and a module including the same. The printed circuit board includes an insulating body, a wiring pattern embedded in the insulating body, and a first conductor pattern disposed on the insulating body and overlapping at least a portion of the wiring pattern in a first direction. First conductive vias each penetrate a portion of the insulating body and are respectively disposed on opposite sides of the wiring pattern, in a second direction orthogonal to the first direction, to surround at least a portion of the wiring pattern. Each first conductive via has a first surface connected to the first conductor pattern, and a second surface, opposite to the first surface, connected to the insulating body.

Abstract: There is provided a fan-out semiconductor device in which a first package having a semiconductor chip disposed therein and having a fan-out form and a second package having a passive component disposed therein and having a fan-out form are stacked in a vertical direction so that the semiconductor chip and the passive component are electrically connected to each other by a path as short as possible.

Abstract: There is provided a fan-out semiconductor device in which a first package having a semiconductor chip disposed therein and having a fan-out form and a second package having a passive component disposed therein and having a fan-out form are stacked in a vertical direction so that the semiconductor chip and the passive component are electrically connected to each other by a path as short as possible.