Patents by Inventor Kwang-kyu Bang
Kwang-kyu Bang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11586538Abstract: Provided is a storage device including a power management integrated circuit chip; multiple non-volatile memories configured to receive power from the power management integrated circuit chip; and a controller configured to control the non-volatile memories, wherein the controller checks a state of the power during a read operation and a write operation on the non-volatile memories and, when a power failure is detected in at least one of the non-volatile memories, implements a power failure detection mode regarding the read operation and the write operation on all of the non-volatile memories.Type: GrantFiled: June 28, 2021Date of Patent: February 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Kyu Bang, Young-Min Kim, Kwan-Bin Yim
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Publication number: 20210326258Abstract: Provided is a storage device including a power management integrated circuit chip; multiple non-volatile memories configured to receive power from the power management integrated circuit chip; and a controller configured to control the non-volatile memories, wherein the controller checks a state of the power during a read operation and a write operation on the non-volatile memories and, when a power failure is detected in at least one of the non-volatile memories, implements a power failure detection mode regarding the read operation and the write operation on all of the non-volatile memories.Type: ApplicationFiled: June 28, 2021Publication date: October 21, 2021Inventors: KWANG-KYU BANG, YOUNG-MIN KIM, KWAN-BIN YIM
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Patent number: 11080186Abstract: Provided is a storage device including a power management integrated circuit chip; multiple non-volatile memories configured to receive power from the power management integrated circuit chip; and a controller configured to control the non-volatile memories, wherein the controller checks a state of the power during a read operation and a write operation on the non-volatile memories and, when a power failure is detected in at least one of the non-volatile memories, implements a power failure detection mode regarding the read operation and the write operation on all of the non-volatile memories.Type: GrantFiled: August 21, 2019Date of Patent: August 3, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Kyu Bang, Young-Min Kim, Kwan-Bin Yim
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Publication number: 20200201762Abstract: Provided is a storage device including a power management integrated circuit chip; multiple non-volatile memories configured to receive power from the power management integrated circuit chip; and a controller configured to control the non-volatile memories, wherein the controller checks a state of the power during a read operation and a write operation on the non-volatile memories and, when a power failure is detected in at least one of the non-volatile memories, implements a power failure detection mode regarding the read operation and the write operation on all of the non-volatile memories.Type: ApplicationFiled: August 21, 2019Publication date: June 25, 2020Inventors: KWANG-KYU BANG, YOUNG-MIN KIM, KWAN-BIN YIM
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Patent number: 9888565Abstract: A memory module includes a module board extending in one direction, a plurality of electronic elements mounted on the module board, and at least one stress detection pattern in a position between the electronic elements or adjacent to one or more of the electronic elements on the module board and including a plurality of strips configured to indicate a stress level generated in the position by an external force applied to the module board.Type: GrantFiled: June 8, 2016Date of Patent: February 6, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Kyu Bang, Yusuf Cinar, Hwi-Jong Yoo
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Publication number: 20170094781Abstract: A memory module includes a module board extending in one direction, a plurality of electronic elements mounted on the module board, and at least one stress detection pattern in a position between the electronic elements or adjacent to one or more of the electronic elements on the module board and including a plurality of strips configured to indicate a stress level generated in the position by an external force applied to the module board.Type: ApplicationFiled: June 8, 2016Publication date: March 30, 2017Inventors: Kwang-Kyu Bang, Yusuf Cinar, Hwi-Jong Yoo
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Patent number: 9372225Abstract: A storage device test system includes: a storage device mounting unit configured to mount a storage device therein; a test control unit configured to transmit and/or receive test signals to and/or from the storage device; an interface plug that is electrically connected to the test control unit and coupled to the storage device mounted in the storage device mounting unit; and a plugging driving unit that controls a relative location between the interface plug and the storage device mounting unit. By using the storage device test system, the causes of defects that may occur while using a storage device may be easily detected.Type: GrantFiled: July 15, 2013Date of Patent: June 21, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-kyu Bang, Min-gwon Moon, Il-do Seo, Yu-hyun Oh
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Publication number: 20140021977Abstract: A storage device test system includes: a storage device mounting unit configured to mount a storage device therein; a test control unit configured to transmit and/or receive test signals to and/or from the storage device; an interface plug that is electrically connected to the test control unit and coupled to the storage device mounted in the storage device mounting unit; and a plugging driving unit that controls a relative location between the interface plug and the storage device mounting unit. By using the storage device test system, the causes of defects that may occur while using a storage device may be easily detected.Type: ApplicationFiled: July 15, 2013Publication date: January 23, 2014Inventors: Kwang-kyu Bang, Min-gwon Moon, Il-do Seo, Yu-hyun Oh
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Patent number: 8379426Abstract: Example embodiments of the inventive concept are directed to solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same, with removable test terminals, which may permit in situ testing of one or more components of the solid state device products.Type: GrantFiled: October 9, 2009Date of Patent: February 19, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-kyu Bang, Kwan-jong Park
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Patent number: 8331175Abstract: According to example embodiments, a solid state drive system includes at least one semiconductor memory, a control circuit including first connection terminals, and second connection terminals. The first connection terminals may be configured to supply one or more operational voltages to the at least one semiconductor memory. The second connection terminals may be configured to supply one or more test voltages to the at least one semiconductor memory.Type: GrantFiled: October 9, 2009Date of Patent: December 11, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-kyu Bang, Kwan-jong Park, Hyun-soo Kim
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Publication number: 20110101495Abstract: A fuse box for a semiconductor device is disclosed and includes a first fuse group comprising a plurality of first fuses, arranged in a first direction and having a first cutting axis, each first fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first and second portions, a second fuse group comprising a plurality of second fuses, arranged in the first direction and having a second cutting axis, each second fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first portion and the second portion, and a third fuse group comprising a plurality of third fuses, wherein each third fuse has either the first cutting axis or the second cutting axis, comprises a first pattern arranged in the first direction and having a first fuse pitch, and a second pattern arranged in a secondType: ApplicationFiled: January 5, 2011Publication date: May 5, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang-kyu BANG, Jong-hyun CHOI
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Patent number: 7888770Abstract: A fuse box for a semiconductor device is disclosed and includes a first fuse group comprising a plurality of first fuses, arranged in a first direction and having a first cutting axis, each first fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first and second portions, a second fuse group comprising a plurality of second fuses, arranged in the first direction and having a second cutting axis, each second fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first portion and the second portion, and a third fuse group comprising a plurality of third fuses, wherein each third fuse has either the first cutting axis or the second cutting axis, comprises a first pattern arranged in the first direction and having a first fuse pitch, and a second pattern arranged in a secondType: GrantFiled: June 18, 2007Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-kyu Bang, Jong-hyun Choi
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Patent number: 7813207Abstract: A fuse box of a semiconductor memory device which comprises a plurality of fuse units commonly connected to a power line, each of the fuse units comprising a first fuse connected with the power line; and a plurality of second fuses connected with the first fuse in parallel. If the second fuses are determined to be cut off, the first fuse is cut off instead of the second fuses.Type: GrantFiled: December 4, 2008Date of Patent: October 12, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Kwang-Kyu Bang
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Patent number: 7804153Abstract: A semiconductor device having a fuse structure that can prevent a bridge between a fuse pattern and a guard ring, and a method of fabricating the same are provided. The fuse pattern formed on a multiple-layered metal interconnect layer is stepped shape increasing a vertical distance between the fuse pattern and the guard ring.Type: GrantFiled: August 23, 2007Date of Patent: September 28, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-kyu Bang, Jun-ho Jang, Yoo-mi Lee
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Publication number: 20100091596Abstract: Example embodiments of the inventive concept are directed to solid state device systems and methods of reducing test times of the same.Type: ApplicationFiled: October 9, 2009Publication date: April 15, 2010Inventors: Kwang-kyu BANG, Kwan-Jong PARK, Hyun-Soo KIM
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Publication number: 20100091539Abstract: Example embodiments of the inventive concept are directed to solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same, with removable test terminals, which may permit in situ testing of one or more components of the solid state device products.Type: ApplicationFiled: October 9, 2009Publication date: April 15, 2010Inventors: Kwang-kyu BANG, Kwan-jong PARK
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Patent number: 7671361Abstract: Provided are a semiconductor device including a fuse focus detector, a fabrication method thereof and a laser repair method. In a chip region, fuses may be formed at a first level. A fuse focus detector including first and second conductive layers may be formed in a scribe line region. The first conductive layer may be formed at the first level, while the second conductive layer may be formed at a different level. For a laser repair method, a target region may be divided into sub-regions. In one selected sub-region, the fuse focus detector may be laser scanned in a direction for a reflection light measurement providing information on a thickness of the fuse focus detector. Using the thickness information, a focus offset value of a fuse in the selected sub-region may be calculated. When the focus offset value is within an allowable range, fuse cutting may be performed.Type: GrantFiled: May 16, 2006Date of Patent: March 2, 2010Assignee: Samsung Electronics Co., LtdInventors: Kwang-kyu Bang, Yong-won Lee, Kyeong-seon Shin, Hyen-wook Ju, Jeong-kyu Kim
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Patent number: 7605444Abstract: Provided are a fuse box that simultaneously prevents damage caused by laser blowing and cross talk between the fuses and a method of manufacturing the same. In a fuse box having an open region in which fuses are opened by laser blowing and a bundle region in which fuse opens do not occur, a capping layer, adjacent to the open region, having a metal layer and an insulation layer covers the outermost fuses in the bundle region, thereby reducing the influence of laser blowing of fuses in the bundle region, and preventing capacitive coupling caused by the formation of a parasitic capacitor between fuse lines and an insulation layer therebetween. Accordingly, cross talk due to the capacitive coupling can be prevented, thereby enhancing the reliability of a fuse circuit. Lower fuses can be disposed in a lower layer in the bundle region, thereby forming a two-layered fuse box.Type: GrantFiled: December 13, 2006Date of Patent: October 20, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-kyu Bang, Kun-gu Lee, Jeong-kyu Kim
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Publication number: 20090141578Abstract: A fuse box of a semiconductor memory device which comprises a plurality of fuse units commonly connected to a power line, each of the fuse units comprising a first fuse connected with the power line; and a plurality of second fuses connected with the first fuse in parallel. If the second fuses are determined to be cut off, the first fuse is cut off instead of the second fuses.Type: ApplicationFiled: December 4, 2008Publication date: June 4, 2009Inventor: Kwang-Kyu Bang
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Patent number: 7492032Abstract: A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.Type: GrantFiled: April 19, 2005Date of Patent: February 17, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Kyu Bang, Kun-Gu Lee, Kyoung-Suk Lyu, Jeong-Ho Bang, Kyeong-Seon Shin, Ho-Jeong Choi, Seung-Gyoo Choi