Abstract: A method for manufacturing a semiconductor package includes disposing a semiconductor chip having contact pads, and a connection structure around the semiconductor chip on a supporting substrate, with the contact pads facing the supporting substrate, forming an encapsulant encapsulating the semiconductor chip and the connection structure on the supporting substrate, embedding a wiring pattern having a connection portion in the encapsulant, the connection portion having a connection hole, forming a through hole penetrating the encapsulant in the connection hole, the through hole exposing a portion of an upper surface of the connection structure, and forming a conductive via in the through hole, the conductive via connecting the wiring pattern to the connection structure.

Abstract: A method for manufacturing a semiconductor package includes disposing a semiconductor chip having contact pads, and a connection structure around the semiconductor chip on a supporting substrate, with the contact pads facing the supporting substrate, forming an encapsulant encapsulating the semiconductor chip and the connection structure on the supporting substrate, embedding a wiring pattern having a connection portion in the encapsulant, the connection portion having a connection hole, forming a through hole penetrating the encapsulant in the connection hole, the through hole exposing a portion of an upper surface of the connection structure, and forming a conductive via in the through hole, the conductive via connecting the wiring pattern to the connection structure.

Abstract: A semiconductor package includes a supporting member that has a cavity and includes a wiring structure connecting first and second surfaces opposing each other. A connection member is on the second surface of the supporting member and includes a first redistribution layer connected to the wiring structure. A semiconductor chip is on the connection member in the cavity and has connection pads connected to the first redistribution layer. An encapsulant encapsulates the semiconductor chip disposed in the cavity and covers the first surface of the supporting member. A second redistribution layer includes wiring patterns embedded in the encapsulant and has exposed surfaces and connection vias that penetrate through the encapsulant to connect the wiring structure and the wiring patterns to each other.

Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.

Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface; a first encapsulant covering at least a portion of each of the inactive surface and side surfaces of the semiconductor chip, and having one or more recessed portions recessed towards the inactive surface of the semiconductor chip; a metal layer disposed on the first encapsulant, and filling at least a portion of each of the recessed portions; and an interconnect structure disposed on the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad. A surface of the metal layer in contact with the first encapsulant has a surface roughness greater than a surface roughness of a surface of the metal layer spaced apart from the first encapsulant.

Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface; a first encapsulant covering at least a portion of each of the inactive surface and side surfaces of the semiconductor chip, and having one or more recessed portions recessed towards the inactive surface of the semiconductor chip; a metal layer disposed on the first encapsulant, and filling at least a portion of each of the recessed portions; and an interconnect structure disposed on the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad. A surface of the metal layer in contact with the first encapsulant has a surface roughness greater than a surface roughness of a surface of the metal layer spaced apart from the first encapsulant.

Abstract: A semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member; and an underbump metallurgy (UBM) layer embedded in the passivation layer and electrically connected to the redistribution layer of the connection member, wherein the UBM layer includes a UBM pad embedded in the passivation layer, at least one plating layer disposed on the UBM pad and having side surfaces of which at least portions are covered by the UBM pad, and a UBM via penetrating through at least portions of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other.

Abstract: An integrated circuit includes a plurality of power rail pairs and a circuit chain. Each of the plurality of power rail pairs includes one of a plurality of high power rails configured to provide a first power supply voltage and one of a plurality of low power rails configured to provide a second power supply voltage that is lower than the first power supply voltage. The circuit chain includes a plurality of unit circuits that are cascade-connected such that an output of a previous unit circuit is provided as an input of a next unit circuit. The plurality of unit circuits are connected distributively to the plurality of power rail pairs.

Abstract: A semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member; and an underbump metallurgy (UBM) layer embedded in the passivation layer and electrically connected to the redistribution layer of the connection member, wherein the UBM layer includes a UBM pad embedded in the passivation layer, at least one plating layer disposed on the UBM pad and having side surfaces of which at least portions are covered by the UBM pad, and a UBM via penetrating through at least portions of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other.

Abstract: A semiconductor package includes a supporting member that has a cavity and includes a wiring structure connecting first and second surfaces opposing each other. A connection member is on the second surface of the supporting member and includes a first redistribution layer connected to the wiring structure. A semiconductor chip is on the connection member in the cavity and has connection pads connected to the first redistribution layer. An encapsulant encapsulates the semiconductor chip disposed in the cavity and covers the first surface of the supporting member. A second redistribution layer includes wiring patterns embedded in the encapsulant and has exposed surfaces and connection vias that penetrate through the encapsulant to connect the wiring structure and the wiring patterns to each other.

Abstract: An integrated circuit includes a plurality of power rail pairs and a circuit chain. Each of the plurality of power rail pairs includes one of a plurality of high power rails configured to provide a first power supply voltage and one of a plurality of low power rails configured to provide a second power supply voltage that is lower than the first power supply voltage. The circuit chain includes a plurality of unit circuits that are cascade-connected such that an output of a previous unit circuit is provided as an input of a next unit circuit. The plurality of unit circuits are connected distributively to the plurality of power rail pairs.

Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.

Abstract: A computer-implemented method of designing an integrated circuit includes: receiving first data that includes a plurality of resistance values with respect to a via in the integrated circuit, wherein each of the plurality of resistance values is defined based on at least one of a width of a conductive line connected to the via or a space between the conductive line and an adjacent conductive line; receiving second data that includes physical characteristics of a layout of the integrated circuit; and extracting, by using a processor, a via resistance based on the layout from the plurality of resistance values based on the first and second data.

Abstract: In a method of analyzing a semiconductor device, output values of semiconductor devices are measured, population data including the output values in connection with values of design attributes of the semiconductor devices is determined, outlier output values are extracted from among the output values included in the population data to determine discriminated data, and a weak value of a weak design attribute, which causes the outlier output values, is determined based on a difference between a ratio of a number of outlier output values, which are related with respective values of the design attributes, to a total number of the outlier output values included in the discriminated data, and a ratio of a number of output values, which are related with respective values of the design attributes, to a total number of the output values included in the population data.

Abstract: A double patterning layout design method includes defining critical paths including a first path and a second path on a schematic circuit, and defining a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit. The defining of the double patterning layout includes anchoring the critical paths on the schematic circuit.

Abstract: A double patterning layout design method comprises defining critical paths comprising a first path and a second path on a schematic circuit, and defining a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit. The defining of the double patterning layout comprises anchoring the critical paths on the schematic circuit.

Abstract: A method of plating a substrate and a method of manufacturing a circuit board using the method of plating a substrate. The method of manufacturing a circuit board may include: providing a panel substrate, the panel substrate divided into a circuit board area and a dummy area; calculating a ratio of an area of a circuit pattern to be formed by plating in the circuit board area; determining a ratio of an area being plated in the dummy area by considering the ratio of the area being plated in the circuit board area; setting a plating part in the circuit board area and the dummy area; and forming the circuit pattern by electroplating the panel substrate. Accordingly, deviation in thickness of plating between circuit patterns can be improved.

Abstract: A method for forming a plating layer and a method for forming a printed circuit board using the same are disclosed. The method for forming a plating layer in accordance with an embodiment of the present invention can include: providing a metal foil coated with a primer resin layer on one surface thereof, roughness formed the one surface of the primer resin layer; transcribing the primer resin layer, on which roughness is formed, to an insulation layer; reducing the primer resin layer so that an anticorrosive material of the metal foil that remains on the primer resin layer is removed; and plating the primer resin layer, on which roughness is formed.

Abstract: A method for manufacturing a printed circuit board with an inner via hole, the method including applying a first current to both surfaces of a core layer having the inner via hole, so that a first plating layer grows centerwardly in an equal rate from all the directions of an inner wall of the inner via hole to close one entrance of the inner via hole, leaving a remaining space the inner via hole unfilled; and applying a second current to fill the remaining space of the inner via hole. Also, the manufacturing method does not require filling an inner via hole with an insulating ink, and forming a conductive layer on the insulating ink. Therefore, the method increases productive capacity and reduces manufacturing cost by simplifying the manufacturing process and reducing the lead time.

Abstract: An aspect of the present invention features a printed circuit board. The board can comprise a core layer in which an inner via hole (IVH) is formed, a first plating layer that closes one entrance of the inner via hole, leaving a remaining space in the inner via hole unfilled; and a second plating layer that closes the other entrance of the inner via hole, filling the remaining space. Also, the present invention provides a printed circuit board and a manufacturing method thereof that do not require filling an inner via hole with an insulating ink, and forming a conductive layer on the insulating ink. Therefore, the present invention can increase productive capacity and reduce manufacturing cost by simplifying the manufacturing process and reducing the lead time.