Patents by Inventor Kwee Chong Chang
Kwee Chong Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9960671Abstract: A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.Type: GrantFiled: December 31, 2014Date of Patent: May 1, 2018Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Dominique Ho, Kwee Chong Chang, Kah Weng Lee, Brian J. Misek
-
Patent number: 9531280Abstract: An isolation device having first and second semiconductor is disclosed. The first semiconductor die may be adapted to transmit a first signal to the second semiconductor die that is electrically isolated. The first semiconductor die may have a transmitter coupled to a modulator that modulates the first signal. The second semiconductor die may have a receiver having a counter and a control circuit. The control circuit may be adapted to determine an indication of the first signal by using the counter. In addition, an isolation system and a DC-DC feedback regulation control system having such control circuit are disclosed. Likewise, a method for conveying a first signal across an isolation barrier is disclosed. The method may comprise counting a received signal based on internal clock and determining an indication of the first signal from the counter's count value.Type: GrantFiled: May 9, 2014Date of Patent: December 27, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Jia Peng, Fun Kok Chow, Chee Heng Wong, Kwee Chong Chang
-
Patent number: 9520920Abstract: Various embodiments of systems for transmitting and receiving a plurality of signals across an isolation material are disclosed. In one embodiment, a first signal may be modulated into a first modulated signal. The first modulated signal is then modulated into a second modulated signal in accordance to a second signal using amplitude modulation. In another embodiment, a first signal and a second signal are modulated into a modulated signal before being modulated further using amplitude modulation. The detection of the modulated signal may be performed using a frequency detector and an amplitude detection circuit that are arranged in parallel. At least some of the apparatuses, circuits, systems and methods disclosed herein may be implemented using conventional CMOS design and manufacturing techniques to provide, for example, at least one or more integrated circuits.Type: GrantFiled: October 27, 2014Date of Patent: December 13, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Gek Yong Ng, Peng Siang Seet, Qian Tao, Kwee Chong Chang
-
Publication number: 20160190918Abstract: A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.Type: ApplicationFiled: December 31, 2014Publication date: June 30, 2016Inventors: Dominique Ho, Kwee Chong Chang, Kah Weng Lee, Brian J. Misek
-
Publication number: 20160119029Abstract: Various embodiments of systems for transmitting and receiving a plurality of signals across an isolation material are disclosed. In one embodiment, a first signal may be modulated into a first modulated signal. The first modulated signal is then modulated into a second modulated signal in accordance to a second signal using amplitude modulation. In another embodiment, a first signal and a second signal are modulated into a modulated signal before being modulated further using amplitude modulation. The detection of the modulated signal may be performed using a frequency detector and an amplitude detection circuit that are arranged in parallel. At least some of the apparatuses, circuits, systems and methods disclosed herein may be implemented using conventional CMOS design and manufacturing techniques to provide, for example, at least one or more integrated circuits.Type: ApplicationFiled: October 27, 2014Publication date: April 28, 2016Inventors: Gek Yong Ng, Peng Siang Seet, Qian Tao, Kwee Chong Chang
-
Publication number: 20150326127Abstract: An isolation device having first and second semiconductor is disclosed. The first semiconductor die may be adapted to transmit a first signal to the second semiconductor die that is electrically isolated. The second semiconductor die may have a receiver having a counter and a control circuit. Each of the first and second semiconductor dies may have a clock generator respectively adapted to generate substantially similar clock frequency in order to transmit or to receive the first signal. In addition, an isolation system and a DC-DC feedback regulation control system having such first and second clock generators are disclosed. Likewise, a method for conveying a first signal across an isolation barrier is disclosed. The method may comprise generating a first clock signal for transmitting the first signal and generating a second clock signal for receiving the first signal.Type: ApplicationFiled: May 9, 2014Publication date: November 12, 2015Applicant: Avago Technologies General lP (Singapore) Pte. Ltd.Inventors: Jia Peng, Fun Kok Chow, Chee Heng Wong, Kwee Chong Chang
-
Publication number: 20150323588Abstract: An isolation device having first and second semiconductor is disclosed. The first semiconductor die may be adapted to transmit a first signal to the second semiconductor die that is electrically isolated. The first semiconductor die may have a transmitter coupled to a modulator that modulates the first signal. The second semiconductor die may have a receiver having a counter and a control circuit. The control circuit may be adapted to determine an indication of the first signal by using the counter. In addition, an isolation system and a DC-DC feedback regulation control system having such control circuit are disclosed. Likewise, a method for conveying a first signal across an isolation barrier is disclosed. The method may comprise counting a received signal based on internal clock and determining an indication of the first signal from the counter's count value.Type: ApplicationFiled: May 9, 2014Publication date: November 12, 2015Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Jia Peng, Fun Kok Chow, Chee Heng Wong, Kwee Chong Chang
-
Patent number: 9000675Abstract: Various embodiments of systems for transmitting and receiving digital and/or analog signals across a single isolator, solid state lighting systems, or DC/DC converter feedback regulation control systems are disclosed. In one embodiment, a first signal may be modulated into a first modulated signal. The first modulated signal is then modulated into a second modulated signal in accordance to a second signal. The second modulated signal is in turn, modulated into a third modulated signal in accordance to a third signal. At least some of the apparatuses, circuits, systems and methods disclosed herein may be implemented using conventional CMOS design and manufacturing techniques and processes to provide, for example, at least one or more integrated circuits.Type: GrantFiled: July 16, 2014Date of Patent: April 7, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Kwee Chong Chang, Jia Peng, Gek Yong Ng, Kok Keong Richard Lum
-
Publication number: 20140328427Abstract: Various embodiments of systems for transmitting and receiving digital and/or analog signals across a single isolator, solid state lighting systems, or DC/DC converter feedback regulation control systems are disclosed. In one embodiment, a first signal may be modulated into a first modulated signal. The first modulated signal is then modulated into a second modulated signal in accordance to a second signal. The second modulated signal is in turn, modulated into a third modulated signal in accordance to a third signal. At least some of the apparatuses, circuits, systems and methods disclosed herein may be implemented using conventional CMOS design and manufacturing techniques and processes to provide, for example, at least one or more integrated circuits.Type: ApplicationFiled: July 16, 2014Publication date: November 6, 2014Inventors: Kwee Chong Chang, Jia Peng, Gek Yong Ng, Kok Keong Richard Lum
-
Patent number: 8847503Abstract: Various embodiments of systems for transmitting and receiving digital and Various embodiments of systems for transmitting and receiving digital and/or analog signals across a single isolator, solid state lighting systems, or DC/DC converter feedback regulation control systems are disclosed. In one embodiment, the digital and analog signals may be modulated into a frequency modulated signal, and each pulse of the frequency modulated signal may be further encoded into a major pulse and a minor pulse. At least some of the circuits, systems and methods disclosed herein may be implemented using conventional CMOS design and manufacturing techniques and processes to provide, for example, a single integrated circuit or ASIC.Type: GrantFiled: April 8, 2013Date of Patent: September 30, 2014Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Kwee Chong Chang, Gek Yong Ng, Richard Kok Keong Lum
-
Publication number: 20130264961Abstract: Various embodiments of systems for transmitting and receiving digital and Various embodiments of systems for transmitting and receiving digital and/or analog signals across a single isolator, solid state lighting systems, or DC/DC converter feedback regulation control systems are disclosed. In one embodiment, the digital and analog signals may be modulated into a frequency modulated signal, and each pulse of the frequency modulated signal may be further encoded into a major pulse and a minor pulse. At least some of the circuits, systems and methods disclosed herein may be implemented using conventional CMOS design and manufacturing techniques and processes to provide, for example, a single integrated circuit or ASIC.Type: ApplicationFiled: April 8, 2013Publication date: October 10, 2013Inventors: Kwee Chong Chang, Gek Yong Ng, Richard Kok Keong Lum
-
Patent number: 8139653Abstract: A galvanic isolator having a transmitting section and a receiving section is disclosed. The transmitting section includes a frame input circuit, a data encoder, and a data transmitter. The frame input circuit receives an input data frame that includes a plurality of input binary bits. The data encoder encodes the input binary bits to generate an encoded data frame that includes a sequence of encoded binary bits in which two successive encoded binary bits represent each input binary bit. The successive encoded binary bits representing a 1 are 01 or 10, and the successive encoded binary bits representing a 0 are 00 or 11. The sequences are chosen to maximize the number of transitions in the encoded data frame. A data receiver recovers the encoded data frame by examining successive pairs of encoded data bits using a clock that is reset on the edges in the encoded data frame.Type: GrantFiled: February 15, 2007Date of Patent: March 20, 2012Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.Inventor: Kwee Chong Chang
-
Patent number: 8116055Abstract: In an opto-isolator, a common mode pulse compensation circuit is provided that senses when a common mode pulse event occurs and that adds current to the LED drive current to compensate for a decrease in the LED drive current caused by the occurrence of the event. The common mode pulse compensation circuit is capable of operating effectively over a very wide range of common mode pulse slopes by automatically adjusting the amount of current that is added to the LED drive current based at least in part on the slope of the sensed common mode pulse. In addition, the common mode pulse compensation circuit is capable of being implemented with LEDs that operate at very low drive currents, which allows the power consumption requirements of the opto-isolator to be reduced.Type: GrantFiled: March 8, 2010Date of Patent: February 14, 2012Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.Inventors: Richard A. Baumgartner, Kwee Chong Chang
-
Patent number: 7760008Abstract: Digital trimming logic is included in a microelectronic device of a type that produces an output signal in response to an input signal and a threshold signal. Trimming logic values are produced in response to a clock signal that is applied to the device in a trimming mode. The clock signal can be applied to a device pin that is used in normal operation to provide an output signal, thus allowing the pin to serve a dual function. The trimming logic changes the trimming logic value in response to the clock signal until the trimming logic value reaches a trim value at which the threshold signal is substantially equal to the input signal. The trimming logic then stores the trim value in a non-volatile memory and enters a locked mode in which further trimming is prevented and the device is ready for normal operation.Type: GrantFiled: October 28, 2008Date of Patent: July 20, 2010Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.Inventors: Jia Peng, Kwee Chong Chang, Shan Jiang
-
Publication number: 20100155627Abstract: In an opto-isolator, a common mode pulse compensation circuit is provided that senses when a common mode pulse event occurs and that adds current to the LED drive current to compensate for a decrease in the LED drive current caused by the occurrence of the event. The common mode pulse compensation circuit is capable of operating effectively over a very wide range of common mode pulse slopes by automatically adjusting the amount of current that is added to the LED drive current based at least in part on the slope of the sensed common mode pulse. In addition, the common mode pulse compensation circuit is capable of being implemented with LEDs that operate at very low drive currents, which allows the power consumption requirements of the opto-isolator to be reduced.Type: ApplicationFiled: March 8, 2010Publication date: June 24, 2010Inventors: Richard A. Baumgartner, Kwee Chong Chang
-
Publication number: 20100105155Abstract: Digital trimming logic is included in a microelectronic device of a type that produces an output signal in response to an input signal and a threshold signal. Trimming logic values are produced in response to a clock signal that is applied to the device in a trimming mode. The clock signal can be applied to a device pin that is used in normal operation to provide an output signal, thus allowing the pin to serve a dual function. The trimming logic changes the trimming logic value in response to the clock signal until the trimming logic value reaches a trim value at which the threshold signal is substantially equal to the input signal. The trimming logic then stores the trim value in a non-volatile memory and enters a locked mode in which further trimming is prevented and the device is ready for normal operation.Type: ApplicationFiled: October 28, 2008Publication date: April 29, 2010Applicant: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.Inventors: Jia Peng, Kwee Chong Chang, Shan Jiang
-
Publication number: 20080198904Abstract: A galvanic isolator having a transmitting section and a receiving section is disclosed. The transmitting section includes a frame input circuit, a data encoder, and a data transmitter. The frame input circuit receives an input data frame that includes a plurality of input binary bits. The data encoder encodes the input binary bits to generate an encoded data frame that includes a sequence of encoded binary bits in which two successive encoded binary bits represent each input binary bit. The successive encoded binary bits representing a 1 are 01 or 10, and the successive encoded binary bits representing a 0 are 00 or 11. The sequences are chosen to maximize the number of transitions in the encoded data frame. A data receiver recovers the encoded data frame by examining successive pairs of encoded data bits using a clock that is reset on the edges in the encoded data frame.Type: ApplicationFiled: February 15, 2007Publication date: August 21, 2008Inventor: Kwee Chong Chang