Patents by Inventor Kwee Lan Tan

Kwee Lan Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9034693
    Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: May 19, 2015
    Assignee: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Il Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario S. Filoteo, Jr.
  • Publication number: 20120018886
    Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.
    Type: Application
    Filed: September 28, 2011
    Publication date: January 26, 2012
    Inventors: Il Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario S. Filoteo, JR.
  • Patent number: 8030783
    Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: October 4, 2011
    Assignee: St Assembly Test Services Ltd.
    Inventors: Il Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario S. Filoteo, Jr.
  • Publication number: 20100038771
    Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.
    Type: Application
    Filed: October 20, 2009
    Publication date: February 18, 2010
    Inventors: Il Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario S. Filoteo, JR.
  • Patent number: 7626277
    Abstract: An integrated circuit package comprises a substrate including a core layer with a through opening and vias. A first conductive layer is on the core layer covering the through opening and a second conductive layer is on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: December 1, 2009
    Assignee: St Assembly Test Services Ltd.
    Inventors: Il Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario S. Filoteo, Jr.
  • Publication number: 20060055009
    Abstract: An integrated circuit package comprises a substrate including a core layer with a through opening and vias. A first conductive layer is on the core layer covering the through opening and a second conductive layer is on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.
    Type: Application
    Filed: November 18, 2005
    Publication date: March 16, 2006
    Applicant: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario Filoteo
  • Patent number: 7008820
    Abstract: A method for manufacturing an integrated circuit package comprises forming a substrate by forming a core layer with a through opening and vias. A first conductive layer is formed on the core layer covering the through opening and a second conductive layer is formed on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are formed between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: March 7, 2006
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Il Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario S. Filoteo, Jr.