Abstract: A mask including a mask substrate including a cell exposure region and a peripheral exposure region, the cell exposure region configured to expose a metal layer in a cell region of a semiconductor device, the peripheral exposure region configured to expose a metal layer in a peripheral region of the semiconductor device, a first mask pattern configured to expose the metal layer in the peripheral exposure region of the mask substrate to form a signal metal pattern, and a second mask pattern configured to expose the metal layer in the peripheral exposure region of the mask substrate to form a dummy metal pattern, the second mask pattern being adjacent to the first mask pattern, and the second mask pattern having a substantially same width as a width of the first mask pattern may be provided.

Abstract: A mask including a mask substrate including a cell exposure region and a peripheral exposure region, the cell exposure region configured to expose a metal layer in a cell region of a semiconductor device, the peripheral exposure region configured to expose a metal layer in a peripheral region of the semiconductor device, a first mask pattern configured to expose the metal layer in the peripheral exposure region of the mask substrate to form a signal metal pattern, and a second mask pattern configured to expose the metal layer in the peripheral exposure region of the mask substrate to form a dummy metal pattern, the second mask pattern being adjacent to the first mask pattern, and the second mask pattern having a substantially same width as a width of the first mask pattern may be provided.

Abstract: The present invention discloses a layout in a semiconductor device having conductive layers electrically connected to conductive regions via contact holes beneath the conductive layers. Each of the conductive layers has a layout with different widths at opposite longitudinal ends thereof, respectively, thereby being capable of achieving an improvement in the alignment margin between the conductive layer and the contact hole within a given memory cell area. Where the layout is applied to capacitors, it is possible to avoid the formation of inferior storage electrodes over regions where contact holes are formed.

Abstract: A layout structure of the interconnection layers of a semiconductor device includes a plurality of conducting lines extending adjacent one another, and at least one rectangular cut-out formed in a side of each of the conducting lines, wherein a width of gap between adjacent ones of the plurality of conducting lines is increased at each rectangular cut-out. The rectangular cut-out serves to increase the space between adjacent conducting lines so as to secure a proper gap there between upon deposition of a passivation layer.

Abstract: A method for manufacturing a capacitor of a semiconductor memory device is provided. A first insulating layer and a second insulating layer are formed in sequence on a semiconductor substrate on which a transistor including a source region, a drain region and a gate electrode, and a buried bit-line surrounded by insulating layer are formed. Then, a contact hole is formed by sequentially etching the layers stacked on the source region, by which the source region of the transistor is exposed, and a spacer made of an insulating substance is formed inside the contact hole, and a first conductive layer is formed on the whole surface of the resultant. Next, the first conductive layer and second insulating layer are etched, and a second conductive layer is formed on the whole surface of the resultant, and a storage electrode is formed by etching the second conductive layer using the first conductive layer as a mask.