Abstract: A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch.

Abstract: A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch.

Abstract: A novel ten-transistor (10-T) content addressable memory (CAM) cell and an integrated CAM architecture. A six-transistor (6-T) static random access memory (SRAM), cell and a four-transistor (4-T) comparator module of the 10-T CAM cell are respectively coupled to different bit lines for preventing any disturbance at a match line associated with the 10-T CAM. Each row of the integrated CAM architecture includes a valid bit cell combined with a protect bit cell and at least a mask cell with global resetting function to sufficiently ensure the correction and flexibility during comparing operations.

Abstract: A novel ten-transistor (10-T) content addressable memory (CAM) cell and an integrated CAM architecture. A six-transistor (6-T) static random access memory (SRAM) cell and a four-transistor (4-T) comparator module of the 10-T CAM cell are respectively coupled to different bit lines for preventing any disturbance at a match line associated with the 10-T CAM. Each row of the integrated CAM architecture includes a valid bit cell combined with a protect bit cell and at least a mask cell with global resetting function to sufficiently ensure the correction and flexibility during comparing operations.

Abstract: A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array and all transistors are initially in an “ON” state. A second dielectric layer covers at least one layer of metal interconnection formed over the first dielectric layer. The bit lines do not overlap the transistor-sources. A coding photoresist layer is formed on the second dielectric layer and is patterned to form a plurality of apertures defining exposure windows exposing underlying field-effect transistors to be coded permanently to an “OFF” state. A code etching back process is implemented using the photoresist layer as a mask to etch the first and second dielectric layers, the sources of the MOSFETs, and a portion of the substrate through the exposure windows to form a deep trench, disconnecting the coded MOSFETs from the source lines.

Abstract: A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array of field-effect transistors. All of the field-effect transistors are initially in an “ON” state having a threshold voltage at a first value. At least one layer of metal interconnection is formed over the first dielectric layer within the ROM region and Is covered by a second dielectric layer. A coding photoresist layer is formed on the second dielectric layer and patterned to form a plurality of apertures defining exposure windows. Using the patterning coding photoresist layer as a dielectric etching and implantation hard mask, the underlying field-effect transistors to be coded permanently to a logic “OFF” state through the apertures, thereby raising the threshold voltage of the field-effect transistors to a second value.

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract: A high voltage NMOS switch is adjustable in order to optimize the switch for proper operation with different circuit configurations. A high voltage booster, included within the high voltage NMOS switch, enables the switch to reclaim the previously unused second half-cycle of a power source waveform signal, which thereby increases the speed of the NMOS switch by a factor of two. In addition, the high voltage NMOS switch provides added ramp rate flexibility by enabling a user to optimize the ramp rate of the high voltage NMOS switch for different circuit configurations.

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract: A single ended sensing scheme amplifies the logic state stored within a non-volatile memory circuit by relying upon three stages, a clamping circuit, a first operational amplifier and a second operational amplifier. The clamping circuit clamps the voltage at a voltage level with a small voltage swing between the logic states. The first stage and second stage operational amplifiers increase the clamped voltage level. A reference memory circuit ensures that the sensing scheme output is properly adjusted to compensate for voltage and temperature variations as well as noise injection from the power supply and ground.

Abstract: A nonvolatile memory cell for a random access memory device is provided. The invented memory cells are similar in configuration to the memory cells of known DRAM devices, so that DRAM devices embodying the invented cells may replace existing DRAM devices. The invented nonvolatile cell also affords a memory device that has low cost of manufacture, high data storage capacity, and low power consumption. Each memory cell includes a floating layer of polysilicon that is interposed between a reference voltage source and a node polysilicon. The floating polysilicon provides nonvolatile storage of data previously stored on the node polysilicon. An electron charge stored on the node polysilicon is transferred to the floating polysilicon, using known electron tunneling methods, before power to the device is removed, so that the data is not lost.

Abstract: A method for fabricating semiconductor devices with a self-spaced contact is provided. Spacing required between the self-spaced contact and a gate region is lessened, thus reducing chip size, and parasitic capacitance and resistance. A transistor region includes a gate and diffusion region. A pad oxide layer comprises an uppermost layer of the gate. A spacer oxide is formed on side walls of the gate region. The thickness of the pad oxide layer controls the width of the spacer oxide region. The spacer oxide insulates the gate from the diffusion regions, so that electrical contacts may be formed close to the gate for reducing the overall size of the semiconductor device. The doping structure of the diffusion regions is controlled by the width of the spacer oxide regions. Thus, the doping structure of the diffusions can be altered to reduce parasitic capacitance and resistance.