Abstract: A Gaussian Frequency Shift Keying/Frequency Shift Keying (GFSK/FSK) modulation circuit implemented in a digital manner comprises a frequency divider for dividing frequency of an inputted clock signal to get a sampling signal, a buffer coupled to the frequency divider for storing inputted data, an integrator coupled to the buffer for processing integration according to the data outputted from the buffer, a first read only memory coupled to the integrator for transferring the data outputted from the integrator according to a cosine function, and a second read only memory coupled to the integrator for transferring the data outputted from the integrator according to a sine function.

Abstract: A frequency shift keying (FSK) demodulator includes a band-pass filter, an auto-calibration loop, a phase comparator, and an analog-to-digital converter. The band-pass filter is used for shifting phase of an FSK signal to generate a revised FSK signal. The auto-calibration loop is coupled to the band-pass filter for adjusting a center frequency of the band-pass filter. The first input end of the phase comparator is coupled to an output end of the band-pass filter, and the second input end of the phase comparator is used for receiving the FSK signal. The phase comparator is used for comparing the FSK signal with the revised FSK signal and outputting a comparison result. The analog-to-digital converter is coupled to the phase comparator for converting the results of the phase comparator into digital data. Similarly, a frequency modulation (FM) demodulator includes a band-pass filter, an auto-calibration loop, and a phase comparator.

Abstract: A packet preamble search method is disclosed for locating a packet preamble with multiple predetermined patterns of a regular form within a received transmission signal with sequential multiple patterns. The pattern of the received transmission signal and the predetermined pattern of the packet preamble have the same length with even bits. The pattern of the transmission signal is sequentially compared with the predetermined pattern. A hit count is increased and a miss count is reset when the pattern of the transmission signal matches the predetermined pattern. The miss count is increased and the hit count is decreased when the pattern of the transmission signal does not match the predetermined pattern. The hit count and the miss count are reset when the hit count is less than or equal to the miss count. An address matching procedure is activated when the hit count exceeds or is equal to a threshold value.

Abstract: A power supply device with power conversion capabilities is disclosed. The power supply device comprises an input module, a power converter, and an output module. The input module is used for receiving an alternating current power. The power converter is coupled to the input module for converting the alternating current power to a direct current power. The output module is coupled to the power converter for outputting the direct current power.

Abstract: A single-ended input to differential-ended output amplifier circuit comprises an amplifier for amplifying an input signal into an amplified signal comprises an input for receiving the input signal; and a first input and a single-ended input to differential-ended output conversion circuit to convert the amplified signal to a differential signal pair, comprising a first transistor for receiving the amplified signal having a first gate coupled to the first output, a first first terminal coupled to a second output, and a first second terminal coupled to a first node; a second transistor having a second gate, a second first terminal coupled to a third input, and a second second terminal coupled to the first node; a second capacitor coupled between the second output and the second gate; a first and a second resistors and the voltage source; and a current source coupled between the first node and a ground.

Abstract: A power supply device with power conversion capabilities is disclosed. The power supply device comprises an input module, a power converter, and an output module. The input module is used for receiving an alternating current power. The power converter is coupled to the input module for converting the alternating current power to a direct current power. The output module is coupled to the power converter for outputting the direct current power.

Abstract: A calibration loop includes an oscillator, an integrator, an amplitude comparator, and a working voltage adjuster. The oscillator is used for generating a reference clock signal. The integrator is coupled to the oscillator for generating an output amplitude according to the reference clock signal and a working voltage. The first input end of the amplitude comparator is coupled to the integrator and the second input end of the amplitude comparator is coupled to the oscillator. The amplitude comparator is used for comparing the output amplitude of the integrator with an amplitude of the reference clock signal of the oscillator and outputting a comparison result. The input end of the working voltage adjuster is coupled to the amplitude comparator, and the output end of the working voltage adjuster is coupled to the integrator. The working voltage adjuster is used for tuning the input working voltage according to the comparison result.

Abstract: A frequency shift keying (FSK) demodulator includes a band-pass filter, an auto-calibration loop, a phase comparator, and an analog-to-digital converter. The band-pass filter is used for shifting phase of an FSK signal to generate a revised FSK signal. The auto-calibration loop is coupled to the band-pass filter for adjusting a center frequency of the band-pass filter. The first input end of the phase comparator is coupled to an output end of the band-pass filter, and the second input end of the phase comparator is used for receiving the FSK signal. The phase comparator is used for comparing the FSK signal with the revised FSK signal and outputting a comparison result. The analog-to-digital converter is coupled to the phase comparator for converting the results of the phase comparator into digital data. Similarly, a frequency modulation (FM) demodulator includes a band-pass filter, an auto-calibration loop, and a phase comparator.

Abstract: A Gaussian Frequency Shift Keying/Frequency Shift Keying (GFSK/FSK) modulation circuit implemented in a digital manner comprises a frequency divider for dividing frequency of an inputted clock signal to get a sampling signal, a buffer coupled to the frequency divider for storing inputted data, an integrator coupled to the buffer for processing integration according to the data outputted from the buffer, a first read only memory coupled to the integrator for transferring the data outputted from the integrator according to a cosine function, and a second read only memory coupled to the integrator for transferring the data outputted from the integrator according to a sine function.

Abstract: A single-ended input to differential-ended output amplifier circuit comprises an amplifier for amplifying an input signal into an amplified signal comprises an input for receiving the input signal; and a first input and a single-ended input to differential-ended output conversion circuit to convert the amplified signal to a differential signal pair, comprising a first transistor for receiving the amplified signal having a first gate coupled to the first output, a first first terminal coupled to a second output, and a first second terminal coupled to a first node; a second transistor having a second gate, a second first terminal coupled to a third input, and a second second terminal coupled to the first node; a second capacitor coupled between the second output and the second gate; a first and a second resistors and the voltage source; and a current source coupled between the first node and a ground.

Abstract: A packet preamble search method for locating a packet preamble with multiple predetermined patterns of a regular form within a received transmission signal with sequential multiple patterns. The pattern of the received transmission signal and the predetermined pattern of the packet preamble have the same length with even bits. The pattern of the transmission signal is sequentially compared with the predetermined pattern. A hit count is increased and a miss count is reset when the pattern of the transmission signal matches the predetermined pattern. The miss count is increased and the hit count is decreased when the pattern of the transmission signal does not match the predetermined pattern. The hit count and the miss count are reset when the hit count is less than or equal to the miss count. An address matching procedure is activated when the hit count exceeds or is equal to a threshold value.