Abstract: A method of forming triple poly silicon split gate flash memory cell comprising of select gate, floating gate, and control gate having the three poly-silicon gates fully aligned with each other is described. High-resolution select-gate poly-silicon-1 is patterned using I-line lithography and resist instead of deep UV (DUV) lithography resist, as is normally used in prior art, which reduces cost of fabrication. Further, the triple poly-silicon structure is etched in a self-aligned manner and also provided with dielectric spacers in the source and drain contact regions prior to forming silicided metal contacts. Self-aligned etching in conjunction with dielectric spacers provide electrical isolation on the drain side and prevent potential bridging between select-gate poly silicon-1 and the drain.