Abstract: Outputting information for recovering a sequence of data is disclosed. Outputting includes making a decision that selects a first sequence of states corresponding to a surviving path, determining a second sequence of states corresponding to a non-surviving path associated with the decision, and defining a possible error event based at least in part on the second sequence of states.

Abstract: Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame using the ECC decoder that includes a faster stage and a slower stage, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed using the ECC decoder.

Abstract: A technique for controlling a group of logic included in a hard disk drive system, is performed by obtaining an access instruction associated with accessing a target location in a disk included in the hard disk system. A number of units until the target location is accessed is calculated. It is determined whether to put the group of logic into a lower power state based at least in part on the number of units until the target location is accessed and a warm up time associated with the group of logic; in the event it is determined to do so, the group of logic is put into the lower power state.

Abstract: A method of obtaining a Viterbi decoded value is disclosed. A decision output is stored to one of a plurality of buffer elements, wherein at least one other buffer element in the plurality is not changing; and data is exposed in the buffer element. A plurality of stored decision outputs is obtained from the plurality of buffers elements. The obtained plurality of stored decision outputs is processed to obtain a Viterbi decoded value.

Abstract: Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder.

Abstract: A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase operation to a portion of a NAND flash memory chip. In the event it is determined to change the value of the voltage threshold, the value of the voltage threshold is changed and the changed value of the voltage threshold and an identifier associated with the portion of the NAND flash memory chip is stored.

Abstract: Processing polynomials is disclosed. At least a portion of processing associated with an error evaluator polynomial and at least a portion of processing associated with an error locator polynomial are performed simultaneously. The error evaluator polynomial and the error locator polynomial are associated with Berlekamp-Massey processing. Data associated with the error evaluator polynomial is progressively removed.

Abstract: Outputting information for recovering a sequence of data is disclosed. Outputting includes making a decision that selects a first sequence of states corresponding to a surviving path, determining a second sequence of states corresponding to a non-surviving path associated with the decision, and defining a possible error event based at least in part on the second sequence of states.