Abstract: The present invention discloses methods and systems for scheduling and distributing power for electric vehicle chargers, through enabling and disabling a plurality of relays at a system. One of the criteria to allow an authenticated user to use an electric vehicle charger is whether there is enough electricity capacity. When the user is allowed to use a scheduled electric vehicle charger, its location is then sent to the user. Alert messages can be generated if charging does not begin within a first time limit and the cancellation of a reservation will take place if the second time limit is reached.

Abstract: Methods of making metal objects are provided. These methods generally involve adding a metal powder slurry into a sacrificial mold, such as a mold made by three dimensional printing, and heating the slurry/mold mixture. The heating steps may include curing the slurry to make a green part inside the mold, debinding to burn off the mold and binder to make a brown part, sintering, and hot isostatic pressing. Metal products, such as aircraft engine parts, are also provided.

Abstract: This invention relates to a method of screening agents for cardiotoxicity based on the observations of the alteration of heart rate and heart rhythm, using teleost embryos and larvae. This invention also relates to a method for identification of gene(s) related to cardiac functions in teleost.

Abstract: This invention relates to a method of 3-tier system for screening compounds, herb extract or extract of herb combination in formula with angiogenic-modulating activities using transparent teleost embryos as model.

Abstract: An advanced fault simulator that can audit the fault coverage of large-scale integrated circuit (IC) designs is described herein. Specifically, an IC design's Hardware Description Language and/or Electronic System-Level source files are compiled into a database, stuck-at, transition and/or inter-process communication faults for the design are generated and equivalent faults are collapsed. Furthermore, all faults are partitioned into disjointed fault sets, and a set of worker threads are created to process those fault sets concurrently. The worker threads can run either locally on a multiprocessor platform, or remotely on different computers that are connected via an intranet and/or the Internet. Moreover, each worker thread can create a plurality of child threads to further accelerate the multithreaded concurrent fault simulation of the IC design. After the simulation is finished, a fault report is generated that depicts the fault coverage of the IC design and all undetected and detected faults.

Abstract: Techniques for performing race logic synthesis on an integrated circuit (IC) are described herein. According to one aspect of the invention, ESL (electronic system level) and any HDL (hardware description language) design source files of an IC design are compiled into a design database. Race logic analysis is performed on the IC design to detect race logic, including race logic for IPC (inter-process communication) and IPS (inter-process synchronization) objects in the IC design, by a third-party tool and/or by the same host EDA (electronic design automation) tool that will be performing race logic synthesis on the IC design, if the latter has built-in race logic audit functions. Based on the race logic audit results, race logic synthesis is performed on the design database, and getting rid of all identified race logic in the IC design, including IPC- and IPS-related race logic.

Abstract: Techniques for performing race logic synthesis on an integrated circuit (IC) are described herein. According to one aspect of the invention, HDL (hardware description language) and/or ESL (electronic system level) design source files of an IC design are compiled into a common design database. Race logic analysis is performed on the IC design, either by a third-party tool or by the same EDA (electronic design automation) tool that also performing race logic synthesis, if the latter has built-in race logic audit functions. Based on the race logic audit results, race logic synthesis is performed on the common design database, and getting rid of all identified race logic in the IC design. This renders the EDA tool can perform concurrent analysis of the IC design, via the race-free common design database, using multi-CPU/core computers and the results will be the same as if the EDA tool had performed serial analysis of the IC design using a single-CPU/core computer.

Abstract: Techniques for performing multiprocessing/multithreaded concurrent fault simulation of large-scale integrated circuit (IC) designs are described herein. Specifically, an IC design's source files, coded in HDL (Hardware Description Language) and/or ESL (Electronic System-Level) languages, are compiled into a database; stuck-at, transition and/or inter-process communication faults are generated and equivalent faults are collapsed. Furthermore, all faults are partitioned into disjointed fault sets, and a plurality of worker processes (or threads) are created to process those fault sets concurrently. The worker processes can run either locally on a multiprocessor platform, or remotely on different computers that are connected via an intranet and/or the Internet. Moreover, each worker process creates a plurality of child threads to carry out the multithreaded concurrent fault simulation of the IC design.

Abstract: A continuous self-cleaning centrifuge assembly having a feed inlet for unclarified liquid and first and second outlets for clarified liquid. Solids are discharged out of a solids holding space in the centrifuge in response to comparison of a measured turbidity to a predetermined turbidity parameter of clarified liquid bled in a detection line in communication with the centrifuge at the second outlet. The turbidity is affected by the degree of build up of solids in the centrifuge. A method of optimizing the clarified liquid outflowing from the centrifuge includes the steps of controlling the flow rate of unclarified liquid into the centrifuge in response to the turbidity of the clarified liquid flowing out of the centrifuge and discharging solids out of a solids holding space in the centrifuge in response to the turbidity measurement.

Abstract: Techniques for performing race logic synthesis on an integrated circuit (IC) are described herein. According to one aspect of the invention, HDL (hardware description language) and/or ESL (electronic system level) design source files of an IC design are compiled into a common design database. Race logic analysis is performed on the IC design, either by a third-party tool or by the same EDA (electronic design automation) tool that also performing race logic synthesis, if the latter has built-in race logic audit functions. Based on the race logic audit results, race logic synthesis is performed on the common design database, and getting rid of all identified race logic in the IC design. This renders the EDA tool can perform concurrent analysis of the IC design, via the race-free common design database, using multi-CPU/core computers and the results will be the same as if the EDA tool had performed serial analysis of the IC design using a single-CPU/core computer.

Abstract: A billing data extraction and processing system for use in connection with a first billing system and a second billing system is disclosed. The billing data extraction and processing system includes a first input to receive rated billing data from the first billing system, a second input to receive rated billing data from the second billing system, and a data processing module, the data processing module responsive to the first input and to the second input, the data processing module processing the aggregated data extracted from at least one of the first and the second billing system. A first set of aggregated billing data at a first point in a billing period of the first billing system and a second set of aggregated billing data at a second point in the billing period of the first billing system are extracted and received at the first input.

Abstract: Techniques a race logic analysis on an integrated circuit (IC) design are described herein. In one embodiment, all hardware description language (HDL) defined system functions and/or tasks that have one or more side-effects when invoked in a first HDL language, but not when the same HDL-defined system functions/tasks are invoked in a second HDL language are identified. For all processing blocks that invoke the HDL-defined system functions/tasks that have side-effects, one or more triggering conditions of the processing blocks and HDL languages in which the processing blocks are coded are collected. When detecting a concurrent invocation race of the HDL-defined system functions/tasks statically or dynamically, checking is performed only the processing blocks that are coded in one or more HDL languages which render the HDL-defined system functions/tasks to manifest the one or more side-effects. Other methods and apparatuses are also described.

Abstract: A continuous self-cleaning centrifuge assembly has a feed inlet (23) to the centrifuge (10) for unclarified liquid, an outlet (29) for clarified liquid, and means (42,39,38) to discharge solids out of a solids holding space (26) in the centrifuge in response to a monitored turbidity parameter of liquid in a detection line (35) in communication with the centrifuge separately from said outlet (29) so that said turbidity is affected by the degree of build up of solids in the centrifuge. In another aspect, a continuous self-cleaning centrifuge assembly has a feed inlet (123) to the centrifuge (110) for unclarified liquid, an outlet (129) for clarified liquid, and means (143,139,138) to discharge solids out of a solids holding space (126) in the centrifuge in response to a monitored turbidity parameter of liquid in an outflow line (128) connected to said outlet (129), wherein said turbidity parameter is the rate of rate of turbidity increase, or second derivative, of the monitored turbidity.

Abstract: A decorative picture mirror is provided. The picture mirror includes a smooth mirror surface. A coating layer is provided on a back portion of the mirror surface, wherein the coating layer covers a select local part of the backside of the mirror surface leaving an uncovered portion of the backside of the mirror surface. A medium including a graphic pattern is connected to the backside of the mirror surface, wherein the graphic pattern substantially fully covers the uncovered portion of the backside of the mirror surface, whereby the coating layer and the graphic pattern form substantially continuous coverage on the select local part of the backside of the mirror surface.

Abstract: This invention relates to a method of 3-tier system for screening compounds, herb extract or extract of herb combination in formula with angiogenic-modulating activities using transparent teleost embryos as model.

Abstract: This invention relates to a method of screening agents for cardiotoxicity based on the observations of the alteration of heart rate and heart rhythm, using teleost embryos and larvae. This invention also relates to a method for identification of gene(s) related to cardiac functions in teleost.

Abstract: A decorative picture mirror is provided. The picture mirror includes a smooth mirror surface. A coating layer is provided on a back portion of the mirror surface, wherein the coating layer covers a select local part of the backside of the mirror surface leaving an uncovered portion of the backside of the mirror surface. A medium including a graphic pattern is connected to the backside of the mirror surface, wherein the graphic pattern substantially fully covers the uncovered portion of the backside of the mirror surface, whereby the coating layer and the graphic pattern form substantially continuous coverage on the select local part of the backside of the mirror surface.

Abstract: Techniques for performing static and dynamic race logic analysis on an integrated circuit (IC) are described herein. According to one aspect of the invention, HDL (hardware description language) design source files of an IC design are compiled into a common design database, including recording full timing information of the IC design. A static race logic analysis is performed on the common design database to reveal all possible race logic in the IC design. A dynamic race logic analysis could also be performed on the common design database to reveal times and circuit locations where the race logic would occur when a physical IC chip for the IC design is implemented. A race logic analysis report is generated for the static and/or dynamic race logic analysis, where the race logic analysis report is used to eliminate race logic errors in IC designs, so as to render highest quality IC products that will not exhibit intermittent random failures in field operations.

Abstract: This invention relates to organic salt compositions useful in the preparation of organoclay compositions, polymer-organoclay composite compositions, and methods for the preparation of polymer nanocomposites. In one embodiment, the present invention provides a pyridinium salt having structure XV wherein Ar6, Ar7, and Ar8 are independently C2-C50 aromatic radicals; “b” is a number from 0 to 2; “d” is a number from 0 to 4; R3 and R4 are independently at each occurrence a halogen atom, a C1-C20 aliphatic radical, a C5-C20 cycloaliphatic radical, or a C2-C20 aromatic radical; Z is a bond, a divalent C1-C20 aliphatic radical, a divalent C5-C20 cycloaliphatic radical, a divalent C2-C20 aromatic radical, an oxygen linking group, a sulfur linking group, a SO2 linking group, or a Se linking group; Ar9 is a C10-C200 aromatic radical, or a polymer chain comprising at least one aromatic group; and X? is a charge balancing counterion.

Abstract: This invention relates to organic salt compositions useful in the preparation of organoclay compositions, polymer-organoclay composite compositions, and methods for the preparation of polymer nanocomposites. In one embodiment, the present invention provides novel organophosphonium salts having structure I wherein Ar1, Ar2, and Ar3 are independently C2-C50 aromatic radicals; Ar4 is a bond or a C2-C50 aromatic radical; “a” is a number from 1 to about 200; “c” is a number from 0 to 3; R1 is independently at each occurrence a halogen atom, a C1-C20 aliphatic radical, a C5-C20 cycloaliphatic radical, or a C2-C20 aromatic radical; R2 is a halogen atom, a C1-C20 aliphatic radical, a C5-C20 cycloaliphatic radical, a C2-C50 aromatic radical, or a polymer chain; and X? is a charge balancing counterion. In another embodiment, the present invention provides methodologies for the preparation of organophosphonium salts having structure I.