Patents by Inventor Kwok Fai Lai

Kwok Fai Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11455345
    Abstract: Document collaboration methods and systems that allow multiple users to create and edit a document are described. Such methods and systems can support devices that receive and process edits to one or more documents while the devices are off-line relative to a document collaboration service. These methods and systems can use a network based storage system (e.g., a “cloud storage platform”) to store a document (e.g., “cloud storage document”) that represents a recent collaboration state of the document based upon edits received from users who are (or have been) using the document collaboration service while one or more other users are off-line.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 27, 2022
    Assignee: Apple Inc.
    Inventors: David A. Underwood, Marcelo Boff, Kwok Fai Lai, Jesse Chapman, Darryl Fuller, Douglas M. Whitmore, Paul D. Zirkle, Benjamin A. C. Forsyth, Chi Yung Tse
  • Publication number: 20210133253
    Abstract: Document collaboration methods and systems that allow multiple users to create and edit a document are described. Such methods and systems can support devices that receive and process edits to one or more documents while the devices are off-line relative to a document collaboration service. These methods and systems can use a network based storage system (e.g., a “cloud storage platform”) to store a document (e.g., “cloud storage document”) that represents a recent collaboration state of the document based upon edits received from users who are (or have been) using the document collaboration service while one or more other users are off-line.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Inventors: David A. Underwood, Marcelo Boff, Kwok Fai Lai, Jesse Chapman, Darryl Fuller, Douglas M. Whitmore, Paul D. Zirkle, Benjamin A.C. Forsyth, Chi Yung Tse
  • Patent number: 7717749
    Abstract: A multiport connector which includes a housing having at least two aligned compartments, each compartment being structured and arranged to receive respective plugs. A multilayer printed wiring board separates the two compartments, the printed wiring board having circuit patterns on opposite sides of opposed non-conductive layers and a metal shielding layer intermediate the non-conductive layers. A first plurality of conductive contact fingers is disposed in one of the compartments, the first plurality of fingers having first portions for making electrical contact with one of the plugs and second portions for making contact with the circuit pattern on one of the non-conductive layers of the multilayer printed wiring board.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: May 18, 2010
    Assignee: Bel Fuse, Inc.
    Inventors: John Chen, Kwok Fai Lai, Kuok Sang Leong, Man Tat Yip, Wai Shun Leung, Chun Wing Ng, Quincy Lee
  • Publication number: 20080264340
    Abstract: A shielding system for a physical vapor deposition chamber having a sputter target above the pedestal. The shielding system comprises a pedestal shield attachable to the pedestal and movable therewith. The pedestal shield surrounds and extends outward from the pedestal toward the chamber side or lower walls. The system also comprises a sidewall shield adapted to extend substantially around and within the chamber sidewalls, and downward from an upper portion thereof. The sidewall shield has a lower end extending inward and disposed adjacent the pedestal shield upper portion when the pedestal is in the raised position. The pedestal shield and sidewall shield cooperate, when the pedestal is in the raised position, to prevent line-of-sight deposition transmission from the sputter target to the side and lower walls of the deposition chamber.
    Type: Application
    Filed: July 8, 2008
    Publication date: October 30, 2008
    Applicant: Novellus Systems, Inc.
    Inventors: Robert Martinson, Norman Bourdon, Kwok Fai Lai, Dhairya Shrivastava, Paul Shufflebothan
  • Patent number: 6905959
    Abstract: A method of depositing thin films comprising tantalum, tantalum nitride, and copper for barrier films and seed layers within high aspect ratio openings used for copper interconnects. The barrier films and seed layers are deposited at extremely low temperature conditions wherein the wafer stage temperature of the sputter source is chilled to about ?70° C. to about 0° C. Most preferably, the present invention is practiced using a hollow cathode magnetron. The resulting tantalum and/or tantalum nitride barrier films and copper seed layers are superior in surface smoothness, grain size and uniformity such that subsequent filling of the high aspect ratio opening is substantially void-free.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: June 14, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Kaihan A. Ashtiani, Maximilian A. Biberger, Erich R. Klawuhn, Kwok Fai Lai, Karl B. Levy, J. Patrick Rymer
  • Patent number: 6541371
    Abstract: A method of depositing thin films comprising tantalum, tantalum nitride, and copper for barrier films and seed layers within high aspect ratio openings used for copper interconnects. The barrier films and seed layers are deposited at extremely low temperature conditions wherein the wafer stage temperature of the sputter source is chilled to about −70° C. to about 0° C. Most preferably, the present invention is practiced using a hollow cathode magnetron. The resulting tantalum and/or tantalum nitride barrier films and copper seed layers are superior in surface smoothness, grain size and uniformity such that subsequent filling of the high aspect ratio opening is substantially void-free.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: April 1, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Kaihan A. Ashtiani, Maximilian A. Biberger, Erich R. Klawuhn, Kwok Fai Lai, Karl B. Levy, J. Patrick Rymer
  • Publication number: 20030022553
    Abstract: A multiport connector which includes a housing having at least two aligned compartments, each compartment being structured and arranged to receive respective plugs. A multilayer printed wiring board separates the two compartments, the printed wiring board having circuit patterns on opposite sides of opposed non-conductive layers and a metal shielding layer intermediate the non-conductive layers. A first plurality of conductive contact fingers is disposed in one of the compartments, the first plurality of fingers having first portions for making electrical contact with one of the plugs and second portions for making contact with the circuit pattern on one of the non-conductive layers of the multilayer printed wiring board.
    Type: Application
    Filed: August 2, 2001
    Publication date: January 30, 2003
    Applicant: Bel-Fuse, Inc.
    Inventors: John Chen, Kwok Fai Lai, Kuok Sang Leong, Man Tat Yip, Wai Shun Leung, Chun Wing Ng, Quincy Lee
  • Patent number: 6342133
    Abstract: Ti and TiN layers are formed on an integrated circuit substrate using a titanium target in non-nitrided mode in a hollow cathode magnetron apparatus. Neither a collimator nor a shield is used. Ti and TiN layers are deposited in vias and trenches having aspect ratios up to 5:1.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: January 29, 2002
  • Publication number: 20010030125
    Abstract: Ti and TiN layers are formed on an integrated circuit substrate using a titanium target in non-nitrided mode in a hollow cathode magnetron apparatus. Neither a collimator nor a shield is used. Ti and TiN layers are deposited in vias and trenches having aspect ratios up to 5:1.
    Type: Application
    Filed: March 14, 2000
    Publication date: October 18, 2001
  • Patent number: 6217716
    Abstract: Magnetic field lines within a hollow cathode magnetron sputtering device are modified by various means to improve the full-face erosion profile of the hollow cathode target. These means include, varying the magnetic field of the main magnetic source, extending the magnetic field beyond the opening in the hollow cathode and adding a stationary or mobile magnetic field source adjacent to the closed end surface of the hollow cathode target. The present invention employs various embodiments which when implemented individually or in combination improve the full face erosion of a target cathode in a hollow cathode magnetron sputtering source.
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: April 17, 2001
    Assignee: Novellus Systems, Inc.
    Inventor: Kwok Fai Lai
  • Patent number: 6193854
    Abstract: A hollow cathode magnetron (HCM) sputter source includes a main magnet positioned near the sidewall of the hollow cathode target and a pair of rotating magnet arrays that are positioned near the closed end of the hollow cathode target. One of the arrays produces a magnetic field that is aligned with (aids) the magnetic field produced by the main magnet; the other arrays produce a magnetic field that is aligned against (bucks) the magnetic field produced by the main magnet. Field lines produced by the magnet arrays contain an extension of the plasma that is controlled by the main magnet. Charged particles circulate between the two portions of the plasma. The extended plasma is thus formed over a very high percentage of the surface of the target, thereby creating an erosion profile that is highly uniform and encompasses essentially the entire face of the target. This maximizes the utilization of the target and minimizes the frequency at which the spent target must be replaced.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: February 27, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: Kwok Fai Lai, Larry Dowd Hartsough, Andrew L. Nordquist, Kaihan Abidi Ashtiani, Karl B. Levy, Maximilian A. Biberger
  • Patent number: 6149050
    Abstract: A method and apparatus for soldering wires of components on PC boards to a lead frame. Wires from the electronic components on a PC board supported by a fixture are led through respective pathways and particularly plated grooves on each side of the PC board. The wires within the pathways are held there by being adhered to a temporary fixture beneath the board until the wires are later affixed in their grooves by dipping the sides of the PC board in a solder pool. The excess wire tails are cut away. The PC board is then mounted on a lead frame, and the leads of the lead frame are aligned with respective pathways of the PC board. The PC board and lead frame are then dipped in solder which electrically connects the wires in their respective pathways to the leads of the lead frame.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: November 21, 2000
    Assignee: Bel Fuse, Inc.
    Inventors: Kwok Fai Lai, Siu-wai Wan, Siu-keung Tse, Jack Xiong Zhenpeng