Abstract: A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.

Abstract: A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.

Abstract: A decoder is disclosed that provides dynamic pipelining of an incoming compressed bitstream. The decoder includes decoding logic modules capable of decoding an incoming compressed bitstream, and memory storing logic in communication with at least one of the decoding modules. Preferably, the memory storing logic is capable of determining whether a memory operation is complete that stores the uncompressed video data to memory. In addition, the decoder includes halting logic in communication with the decoding logic and the memory storing logic. The halting logic halts the decoding of the incoming bitstream during a specific time period, which includes a time period wherein the memory operation is incomplete. Finally, initiating logic is included in the decoder that is in communication with the decoding logic and the memory storing logic. The initiating logic of the decoder restarts the decoding when the memory operation is complete.

Abstract: A decoder for decoding a compressed incoming interruptible bitstream is disclosed. The decoder includes an input register that is capable of receiving a latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. The decoder also includes decoding logic, such as variable length decoding logic, or run-length decoding logic, in communication with the input register. Further included in the decoder is an output register in communication with decoding logic, that is also capable of receiving the latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. Finally, the decoder includes a register controller in communication with both the input register and the output register. The register controller is capable of receiving a halt command from the system and, upon receiving the halt command, the register controller sends the latch command to both the input register and the output register.

Abstract: Disclosed is a partitioning procedure for designing MPEG decoders, AC-3 decoders, and decoders for other audio/video standards. The procedure provides that some specified decoding functionality be implemented exclusively in the form of hardware and certain other specified decoding functionality be provided exclusively as firmware or software. A video decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, video header processing functions; and (b) hardware for implementing preparsing assist, macroblock reconstruction, and video display control functions. An audio decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, decoding fields containing parameters for processing the audio data; and (b) hardware for implementing matrixing and windowing functions on the audio data.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream includes macroblocks of video data which can each include input Motion Compensation (M) data and input discrete cosine Transform Coded (I) data. A motion pipeline processes the input M data to produce processed M data, and a transform pipeline processes the input I data to produce processed I data. A controller controls the motion pipeline and the transform pipeline to concurrently process the input M data and the input I data respectively such that a length of time required for processing each macroblock is variable and is determined by the largest of a length of time required for the motion pipeline to process the input M data and a length of time required for the transform pipeline to process the input I data of the macroblock.

Abstract: A tri-state driver circuit is disclosed which provides rail-to-rail output swings and does not consume a significant amount of d.c. power.

Abstract: BiCMOS circuits are disclosed which achieve high speed operation under a wide range of loading conditions. The circuits are capable of providing a full output voltage swing and dissipate virtually no static power. The BiCMOS circuits are implemented using both CMOS and bipolar transistors. The circuits use their output signal to control the CMOS transistors that overcome bipolar output drops for full swing operation. The same fundamental CMOS and bipolar configurations can be applied to implement complex and simple logic functions such as NAND, NOR, AND, or OR operations.

Abstract: An N-bit conditional sum adder 8 includes first and second conditional sum adders 10a and 10b. Each of the adders may be built from a plurality of one-bit conditional sum adders 110. In one embodiment, each one-bit adder 110 comprises a XNOR gate 50, a XOR gate 52, a NAND gate 54 and a NOR gate 56. The carry outputs CO.sub.a and CO.sub.b of the first conditional sum adder 10.sub.a are coupled to BiCMOS drivers 12 and 14 which in turn are coupled to the select inputs of a plurality of multiplexers 16 and 18. The multiplexers may be CMOS multiplexers built from transmission gates.