Abstract: Some embodiments of the invention provide a method for inserting several fills in an integrated circuit (“IC”) layout. The method identifies a set of potential fills in a region of an IC layout, where the set of potential fills has a first fill size, wherein the first fill size is from a set of fill sizes. The method specifies a halo around each potential fill in the set of potential fills. For each potential fill, the method determines whether the specified halo overlaps with a foreign object in the region of the layout. For each potential fill, the method specifies a legal fill in the region of the IC layout if the specified halo does not overlap with a foreign object in the region of the IC layout. The method inserts at least one legal fill in the region of the IC layout. In some embodiments, the halo is a spacing halo.

Abstract: Some embodiments of the invention provide a method for inserting several fills in an integrated circuit (“IC”) layout. The method identifies a set of potential fills in a region of an IC layout, where the set of potential fills has a first fill size, wherein the first fill size is from a set of fill sizes. The method specifies a halo around each potential fill in the set of potential fills. For each potential fill, the method determines whether the specified halo overlaps with a foreign object in the region of the layout. For each potential fill, the method specifies a legal fill in the region of the IC layout if the specified halo does not overlap with a foreign object in the region of the IC layout. The method inserts at least one legal fill in the region of the IC layout. In some embodiments, the halo is a spacing halo.

Abstract: Some embodiments of the invention provide a method for inserting several fills in an integrated circuit (“IC”) layout. The method identifies a set of potential fills in a region of an IC layout, where the set of potential fills has a first fill size, wherein the first fill size is from a set of fill sizes. The method specifies a halo around each potential fill in the set of potential fills. For each potential fill, the method determines whether the specified halo overlaps with a foreign object in the region of the layout. For each potential fill, the method specifies a legal fill in the region of the IC layout if the specified halo does not overlap with a foreign object in the region of the IC layout. The method inserts at least one legal fill in the region of the IC layout. In some embodiments, the halo is a spacing halo.

Abstract: The present invention provides a local rip-up and reroute (LRR) method to reduce the number of open nets after the initial routers have been applied. Two main tasks are performed under this method. The first task is to identify a locally blocked pin and rip up wire segments in an area around the cell having the locally blocked pin. The second task is to reroute the now freed locally blocked pin. In the first task, an open net is read from the list of open nets. The pins of this open net are identified and determined if they are locally blocked. A pin is considered as locally blocked if a routing path, starting from the pin, cannot be found within N grid point expansions. If a pin is locally blocked, segments of wires within or at the boundary of a predefined bounding box are removed (or ripped-up)--except for two situations. The first exception is that a wire that is connected to a pin is not ripped-up.

Abstract: A microelectronic circuit includes a plurality of circuitry blocks and sub-blocks, a clock driver, an electrical interconnect that directly connects the clock driver to the sub-blocks, and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively. A method of producing a hierarchial clock distribution system for the circuit includes determining clock skews between the clock driver and the sub-blocks respectively. Delay buffers are selected from a predetermined set of delay buffers having the same physical size and different delays, with the delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively. Each delay buffer includes a delay line, and a number of loading elements that are connected to the delay line, with the number of loading elements being selected to provide the required clock delay for the respective sub-block.