Patents by Inventor Kwok W. Yeung
Kwok W. Yeung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9529744Abstract: A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface.Type: GrantFiled: June 16, 2014Date of Patent: December 27, 2016Assignee: SK hynix memory solutions Inc.Inventors: Kwok W. Yeung, Meng-Kun Lee, Gubo Huang
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Patent number: 9419748Abstract: A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.Type: GrantFiled: August 7, 2014Date of Patent: August 16, 2016Assignee: SK Hynix memory solutions Inc.Inventors: Kwok W. Yeung, Kin Man Ng, Kin Ming Chan
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Patent number: 9142323Abstract: A method for correcting a cell voltage driftage in a NAND flash device is disclosed. An indicator indicating a cell voltage driftage in a memory unit of a NAND flash device is monitored by a processor. A cell voltage driftage in the NAND flash device is detected based at least in part on the indicator. One or more NAND commands correcting the cell voltage driftage are generated. The one or more NAND commands include a NAND command associated with changing a configuration setting of the NAND flash device.Type: GrantFiled: February 29, 2012Date of Patent: September 22, 2015Assignee: SK hynix memory solutions inc.Inventors: Meng-Kun Lee, Kwok W. Yeung
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Patent number: 9058290Abstract: Accessing data at a memory is described. A request associated with a read or write operation is received, wherein the request includes a logical address associated with the memory. A physical address is generated based at least in part on the logical address. A block of data at the memory that includes data associated with the physical address is determined. Data at the determined block of data and a corresponding set of ECC from the memory are accessed. Whether the accessed data can be decoded based at least in part on the corresponding set of ECC is determined.Type: GrantFiled: April 28, 2014Date of Patent: June 16, 2015Assignee: SK hynix memory solutions inc.Inventors: Ka Hou Chan, Kwok W. Yeung
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Patent number: 9043688Abstract: Generating error data associated with decoding data is disclosed, including: processing an input sequence of samples associated with data stored on media using a detector and a decoder during a global iteration; and generating one or more error values based at least in part on one or more decision bits output by the detector or the decoder and the input sequence of samples.Type: GrantFiled: March 22, 2012Date of Patent: May 26, 2015Assignee: SK hynix memory solutions inc.Inventors: Kai Keung Chan, Xin-Ning Song, Jason Bellorado, Kwok W. Yeung
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Publication number: 20150033093Abstract: A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.Type: ApplicationFiled: August 7, 2014Publication date: January 29, 2015Inventors: Kwok W. Yeung, Kin Man Ng, Kin Ming Chan
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Patent number: 8918696Abstract: A method for decoding data is disclosed. The method includes partitioning a low-density parity check (LDPC) matrix into a plurality of groups, each comprising one or more check node layers. The method further includes selecting one of the groups based at least in part on a cost function, the cost function based at least in part on information associated with a variable node, or information associated with a check node, or both. The method further includes performing LDPC layered decoding on the selected group.Type: GrantFiled: April 11, 2011Date of Patent: December 23, 2014Assignee: SK hynix memory solutions inc.Inventors: Kin Man Ng, Kwok W. Yeung, Lingqi Zeng, Yu Kou, Aditi R. Ganesan
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Publication number: 20140365716Abstract: A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface.Type: ApplicationFiled: June 16, 2014Publication date: December 11, 2014Inventors: Kwok W. Yeung, Meng-Kun Lee, Gubo Huang
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Publication number: 20140325313Abstract: Accessing data at a memory is described. A request associated with a read or write operation is received, wherein the request includes a logical address associated with the memory. A physical address is generated based at least in part on the logical address. A block of data at the memory that includes data associated with the physical address is determined. Data at the determined block of data and a corresponding set of ECC from the memory are accessed. Whether the accessed data can be decoded based at least in part on the corresponding set of ECC is determined.Type: ApplicationFiled: April 28, 2014Publication date: October 30, 2014Applicant: SK hynix memory solutions inc.Inventors: Ka Hou Chan, Kwok W. Yeung
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Patent number: 8862971Abstract: Inter-track-interference correlation and cancellation for disk drive application includes receiving an input sequence of samples; and simultaneously processing the input sequence in at least a detector over one or more iterations while processing the input sequence to produce inter-track-interference information during at least a portion of one of the one or more iterations.Type: GrantFiled: June 22, 2011Date of Patent: October 14, 2014Assignee: SK hynix memory solutions inc.Inventors: Kai Keung Chan, Xin-Ning Song, Kwok W. Yeung, Xianfeng Rui
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Patent number: 8839051Abstract: A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.Type: GrantFiled: February 24, 2012Date of Patent: September 16, 2014Assignee: SK hynix memory solutions inc.Inventors: Kwok W. Yeung, Kin Man Ng, Kin Ming Chan
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Patent number: 8804264Abstract: Calibrating a read channel is disclosed. Previously written user data is read from an auxiliary memory. The previously written user data is processed through a plurality of write channel stages. The output of at least one of the plurality of write channel stages is compared to the output of a corresponding read channel stage to generate an error signal.Type: GrantFiled: May 31, 2012Date of Patent: August 12, 2014Assignee: SK hynix memory solutions inc.Inventors: Kwok W. Yeung, Xin-Ning Song
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Patent number: 8793419Abstract: A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface.Type: GrantFiled: November 1, 2011Date of Patent: July 29, 2014Assignee: SK hynix memory solutions inc.Inventors: Kwok W. Yeung, Meng-Kun Lee, Gubo Huang
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Patent number: 8719664Abstract: Accessing data at a memory is described. A request associated with a read or write operation is received, wherein the request includes a logical address associated with the memory. A physical address is generated based at least in part on the logical address. A block of data at the memory that includes data associated with the physical address is determined. Data at the determined block of data and a corresponding set of ECC from the memory are accessed. Whether the accessed data can be decoded based at least in part on the corresponding set of ECC is determined.Type: GrantFiled: October 13, 2011Date of Patent: May 6, 2014Assignee: SK hynix memory solutions inc.Inventors: Ka Hou Chan, Kwok W. Yeung
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Patent number: 8671335Abstract: A first sequence of states associated with a surviving path and a second sequence of states associated with a non-surviving path are determined. A possible error event is determined based at least in part on the first sequence of states and the second sequence of states. The first sequence of states is replaced with the second sequence of states by applying the possible error event to the first sequence of states.Type: GrantFiled: January 2, 2013Date of Patent: March 11, 2014Assignee: SK hynix memory solutions inc.Inventors: Kwok W. Yeung, Shih-Ming Shih
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Patent number: 8659847Abstract: User level data associated with a location adjacent to a desired location on a magnetic disk storage is received. Media level data associated with the adjacent location is generated based at least in part on the user level data associated with the adjacent location; a processor which is configured to generate the media level data associated with the adjacent location is a same processor which is configured to generate media level data based at least in part on user level data during a write process. The media level data associated with the adjacent location is used to remove inter-track interference (ITI) associated with the adjacent location from a signal read back from the desired location.Type: GrantFiled: February 7, 2012Date of Patent: February 25, 2014Assignee: SK hynix memory solutions inc.Inventors: Kwok W. Yeung, Kin Man Ng, Kin Ming Chan
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Patent number: 8650453Abstract: A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes.Type: GrantFiled: February 28, 2013Date of Patent: February 11, 2014Assignee: SK hynix memory solutions inc.Inventors: Kin Man Ng, Lingqi Zeng, Yu Kou, Kwok W. Yeung
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Patent number: 8599621Abstract: An instruction to perform an erase on a group of one or more memory cells is sent. An indication that the erasure of the group of memory cells is unsuccessful is received. In response to receiving the indication that the erasure of the group of memory cells is unsuccessful, the value of a voltage threshold, associated with the group of memory cells, is changed to a new voltage threshold and the new voltage threshold and identification information associated with the group of memory cells is stored.Type: GrantFiled: February 4, 2013Date of Patent: December 3, 2013Assignee: SK hynix memory solutions inc.Inventors: Kwok W. Yeung, Meng-Kun Lee
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Patent number: 8570680Abstract: Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel.Type: GrantFiled: May 23, 2011Date of Patent: October 29, 2013Assignee: SK hynix memory solutions inc.Inventors: Kwok W. Yeung, Kai Keung Chan, Paul K. Lai
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Patent number: 8572471Abstract: Decoding is performed on input data to obtain first decoded data using a first error correction decoder. If decoding by a second error correction decoder on the first decoded data fails, decoding is performed using an output of the second decoder and using the first decoder. A reservation request is sent from the second error correction decoder to a memory prior to completion of the decoding on the first decoded data. Space is reserved in the memory in response to receiving the reservation request from the second decoder.Type: GrantFiled: October 19, 2012Date of Patent: October 29, 2013Assignee: SK hynix memory solutions inc.Inventors: Kwok W. Yeung, Kin Man Ng