Patents by Inventor KwokKeung Szeto

KwokKeung Szeto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of stacking semiconductor die on a fan-out WLCSP
    Patent number: 9478485
    Abstract: A semiconductor device has a first semiconductor die. A first interconnect structure, such as a conductive pillar including a bump formed over the conductive pillar, and second interconnect structure are formed in a peripheral region of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die between the first interconnect structure and the second interconnect structure. A height of the second semiconductor die is less than a height of the first interconnect structure. A footprint of the second semiconductor die is smaller than a central region of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and second semiconductor die. Alternatively, the second semiconductor die is disposed over a semiconductor package including a plurality of interconnect structures. External connectivity from the single side fo-WLCSP is performed without the use of conductive vias to provide a high throughput and device reliability.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: October 25, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: XuSheng Bao, KwokKeung Szeto
  • Semiconductor Device and Method of Stacking Semiconductor Die on a Fan-Out WLCSP
    Publication number: 20150001709
    Abstract: A semiconductor device has a first semiconductor die. A first interconnect structure, such as a conductive pillar including a bump formed over the conductive pillar, and second interconnect structure are formed in a peripheral region of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die between the first interconnect structure and the second interconnect structure. A height of the second semiconductor die is less than a height of the first interconnect structure. A footprint of the second semiconductor die is smaller than a central region of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and second semiconductor die. Alternatively, the second semiconductor die is disposed over a semiconductor package including a plurality of interconnect structures. External connectivity from the single side fo-WLCSP is performed without the use of conductive vias to provide a high throughput and device reliability.
    Type: Application
    Filed: April 24, 2014
    Publication date: January 1, 2015
    Applicant: STATS ChipPAC, Ltd.
    Inventors: XuSheng Bao, KwokKeung Szeto