Abstract: A high-speed bit synchronizer comprising a phase comparator for detecting a phase relationship between a center of an eye pattern of input NRZ data and a rising transition of a clock pulse from a voltage controlled oscillator (VCO) whenever the input NRZ data makes a transition, a frequency comparator for detecting a frequency relationship between a multiple of a period of the clock pulse from the VCO and a multiple of a period of an external reference clock pulse whenever the external reference clock pulse makes a rising or falling transition, phase and frequency comparator gain limiters for limiting gains of the phase and frequency comparators, respectively, a frequency synchronous signal detector for generating frequency synchronous and asynchronous signals in response to an output of the frequency comparator, a phase difference output controller for controlling the transfer of an output of the phase comparator gain limiter in response to an output of the frequency synchronous signal detector, a low pass f

Abstract: A bit synchronizer for NRZ data wherein a loop gain of a phase locked loop in the bit synchronizer is not varied sensitively to bit pattern and rate of the NRZ data and a voltage control led oscillator in the bit synchronizer oscillates synchronously with a multiple of a frequency of an external reference clock pulse even in the absence of NRZ data transitions or over a wide range of variation of a clock frequency of the voltage controlled oscillator, so that the NRZ data and clock can be recovered stably, According to the invention, the bit synchronizer comprises a phase comparator, a first gain controller, a frequency comparator, a second gain controller, a N-frequency divider, a low pass filter and a voltage controlled oscillator.

Abstract: A phase comparing and CMI/NRZ decoding apparatus for accomplishing bit synchronization of CMI data by producing rising transition or falling transition of the clock pulse at the center of unit bit interval of incoming CMI data, by use of the clock pulse having a period equivalent to 2 unit bit intervals of CMI data, and for realizing stable decoding of CMI data to NRZ data. This apparatus is implemented by means of a data output means 2, a clock pulse generating means 1 for generating in-phase and inverse-phase pulses, a inter-transitions time interval information output means 3 for outputting information about line interval between the data transition and the clock pulse transition, a reference pulse generating means 4, a falling transition detecting and 3-step half-period shifting means 6, a rising transition detecting and 2-step half-period shifting means 5, a CMI/NRZ decoding circuit 7 and a code violation detecting means 8.

Abstract: The present invention provides a phase detector comprising a driver U1 and D-type flip-flops U2 and U3 which reduces the high frequency component of the jitter in VCO, in analog-fashion operation, enables the use of general purpose logic elements being irrespective of the data bit speed, and enables the application of both analog PLL and digital PLL.

Abstract: The object of the present invention is to provide a phase detector comprising three D-type flip-flops, which compares the transition phase of retiming clock pulses with the phase of the center of the unit bit interval of received data, produces the compared result in digital fashion to operate irrespective of the data bit speed and in the form of a phase information that is compatible with a digital circuit.

Abstract: A frequency and phase detection circuit in an NRZ bit synchronous system by simultaneously retiming an NRZ input with an in-phase clock and an inverse-phase clock, respectively. A first frequency and phase difference is extracted by supplying the retimed NRZ with the in-phase clock and the delay-compensated NRZ input to an exclusive OR-gate. A second frequency and phase difference is extracted by supplying the retimed NRZ with the inverse-phase clock and the retimed NRZ with the in-phase clock to another exclusive OR-gate.

Abstract: A NRZ/CMI (II) code converter comprising a D-type flip-flop for retiming a series of NRZ data bits received thereto with a clock synchronized therewith, an OR-gate connected to said one output of the D-type flip-flop to compose space bits of a series of said received NRZ data bits and a transmitted clock, and a delay element connected to the output of said OR-gate. The converter also comprises another OR gate connected to a negative output of said D-type flip-flop and another D-type flip-flop having a clock input connected to the output of said OR-gate. These elements function to compose mark bits of a series of the NRZ data bits with clock pulses and to generate two-divided alternative mark bits.An exclusive OR-gate is connected to the output of said another OR-gate and the output of said another D-type flip-flop.

Abstract: A reframe circuit in a synchronous multiplexing device comprising a frame synchronizing pattern detection circuit, a frame pattern bit error detection circuit responsive to a serial data stream from the frame synchronizing pattern detection circuit, an in-frame/out-of-frame state discrimination circuit responsive to the output signal from the frame pattern bit error detection circuit and the output signal from the synchronizing pattern detection circuit, a counter phase synchronizing circuit responsive to the output signal from the in-frame/out-of-frame state discrimination circuit, the output signal from the frame synchronization pattern detection circuit and a reference phase signal, and a counter and timing generation circuit responsive to the operating mode control signal from the counter phase synchronizing circuit.