Abstract: A method for forming a low resistance metal/polysilicon gate for use in CMOS devices comprising: (1) a novel anneal step prior to formation of a diffusion barrier layer and (2) a novel diffusion barrier layer composed of titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon. A first insulating layer is formed over a silicon substrate, and a polysilicon layer is formed over the first insulating layer. In a key step, the polysilicon layer is annealed to prevent peeling of the subsequently formed diffusion barrier layer. A diffusion barrier layer comprising titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon is formed over the polysilicon layer. A tungsten layer is formed over the diffusion barrier layer, and a capping layer comprising a silicon nitride layer over an oxide layer can be formed over the tungsten layer.

Abstract: The present invention discloses a method to manufacture metal gate of integrated circuits. A gate oxide layer is formed on a substrate and a polysilicon layer is then deposited on the gate oxide layer. Afterwards, a barrier layer is formed on the polysilicon layer and a metal layer is deposited on the barrier layer. An etching process is performed to etch the metal layer and the barrier layer, and a metal gate is defined. Then, silicon nitride liners are formed on the sidewalls of the metal gate. Finally, silicon nitride spacers are formed on the silicon nitride liners and on the sidewalls of the polysilicon gate to serve as an insulating layer.

Abstract: A method was achieved for forming a multilayer passivation layer comprised of a silicon oxide/silicon nitride/silicon oxide/silicon nitride by depositing the layers consecutively in a single PECVD system. The method consists of depositing a first SiO.sub.2 layer that serves as a stress-release layer, a thin Si.sub.3 N.sub.4 layer that serves as a buffer layer that minimizes cracking and as a passivation layer that prevents mobile alkaline ion penetration, a thin second SiO.sub.2 layer to fill and seal any remaining cracks and pinholes in the first Si.sub.3 N.sub.4 layer, and a main Si.sub.3 N.sub.4 passivation layer that prevents water and/or other corrosive chemicals from attacking the metal. Since this multilayer passivation layer can be deposited essentially pinhole-free to a thickness that is less than the prior art's passivation layer of 8000 Angstroms needed to prevent pinholes, it can be used on 0.38 to 0.

Abstract: A plasma treatment method used to form improved PECVD silicon nitride film passivation layers over metal interconnections on ULSI circuits is achieved. The process is carried out in a single PECVD reactor. After depositing a thin silicon oxide stress-release layer over the metal lines, a plasma-enhanced CVD silicon nitride layer is deposited, and subsequently a plasma treatment step is carried out on the silicon nitride layer. The use of a sufficiently thin silicon nitride layer eliminates photoresist trapping at the next photoresist process step that would otherwise be trapped in the voids (keyholes) that typically form in the silicon nitride passivation layer between the closely spaced metal lines, and can cause corrosion of the metal. The plasma treatment in He, Ar, or a mixture of the two, is then used to densify the silicon nitride layer and to substantially reduce pinholes that would otherwise cause interlevel metal shorts.

Abstract: A metal layer (24) is formed on an isolation layer (22) to act as interconnections. Subsequently, a thin liner layer (26) is optionally formed along the surface of the metal layer (24) to serve as a buffer layer. An undoped silicate glass (USG) layer (28) is deposited on the liner layer (26). The USG layer (28) is formed using ozone and tetraethylorthosilicate (TEOS) as a source at a temperature of approximately 380 to 420.degree. C. Oxygen gas is used as a carrier for the ozone. The flow rate of the oxygen gas is approximately 4000 to 6000 sccm. Helium gas is used as a carrier for the TEOS. The flow rate of the helium is approximately 3000 to 5000 sccm. A silicon nitride layer (30) is deposited on the USG layer (28) using plasma enhanced chemical vapor deposition (PECVD). The silicon nitride layer (30) serves as a main passivation layer. The thickness of the silicon nitride layer (30) is approximately 3000 to 7000 angstroms.

Abstract: A method was achieved for forming a multilayer passivation layer comprised of a silicon oxide/silicon nitride/silicon oxide/silicon nitride by depositing the layers consecutively in a single PECVD system. The method consists of depositing a first SiO.sub.2 layer that serves as a stress-release layer, a thin Si.sub.3 N.sub.4 layer that serves as a buffer layer that minimizes cracking and as a passivation layer that prevents mobile alkaline ion penetration, a thin second SiO.sub.2 layer to fill and seal any remaining cracks and pinholes in the first Si.sub.3 N.sub.4 layer, and a main Si.sub.3 N.sub.4 passivation layer that prevents water and/or other corrosive chemicals from attacking the metal. Since this multilayer passivation layer can be deposited essentially pinhole-free to a thickness that is less than the prior art's passivation layer of 8000 Angstroms needed to prevent pinholes, it can be used on 0.38 to 0.