Abstract: Pin-to-pin electro-static-discharge (ESD) protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain. A p-type substrate is normally pumped below ground by a substrate bias generator when power is applied. However, during a pin-to-pin ESD test, power and ground are floating. A gate node is pulled high through a coupling capacitor by the ESD pulse. The gate node turns on a shunting transistor to couple the ESD pulse to the floating ground bus. The gate node also turns on a shorting transistor that connects the floating ground bus to the floating substrate. A resistor drains the coupling capacitor to the substrate, rather than to ground. Current is injected into the substrate by the resistor. The snapback voltage is lowered by substrate-triggering.

Abstract: A bus switch has an n-channel bus-switch transistor between two buses and a p-channel pullup transistor. When power is disconnected from the bus switch, and one bus is hot and has a voltage above ground, this higher voltage is conducted to the gate and substrate of the p-channel pullup transistor. This biasing keeps the p-channel transistor turned off. When power is off, a connecting p-channel transistor connects the higher voltage on the hot bus to the p-channel gate node, while an inverting p-channel transistor connects the gate node to the substrate under the p-channel transistor. Inverting transistors receive an inverse enable signal and drive the gate node when power is applied, turning on the pullup transistor when the n-channel bus-switch transistor is off, and vice-versa. The gate node is fed back and applied to the gate of a source transistor that connects power to the substrate.

Abstract: A clock driver chip has several banks of clock outputs driven by a single clock reference. Each clock output is driven by large pull-up and pull-down transistors, which have gates driven by pre-driver lines generated by a pre-driver circuit. Individual clock outputs, or a bank of outputs, are enabled by enable signals. A shorting switch is activated when enables for a pair of clock outputs are in a same state. The shorting switch has two transmission gates. One transmission gate shorts the pre-driver lines to the large p-channel transistors of the pair of outputs, while the other transmission gate shorts the pre-driver lines to the large n-channel transistors of the pair of outputs. Pre-driver lines to the pull-up transistors within a bank driven by the same enable can be hardwired together, as can the pre-driver lines to the pull-down transistors. Shorting switches can short banks together to reduce output skew.

Abstract: An active terminating circuit has buffers to produce wider voltage drives on clamping transistors. A transmission line drives coupling capacitors. One capacitor drives an upper node that drives the gate of an upper buffer transistor. The upper buffer transistor drives a p-gate node coupled to a gate of a p-channel clamping transistor. The other capacitor drives a lower node that drives the gate of a lower buffer transistor, which drives an n-gate node of an n-channel clamping transistor. The drains of the clamping transistors are connected to the transmission line. Resistors pull the lower node to the power-supply voltage and pull the upper node to ground when no transitions occur on the transmission line, achieving zero standby power. When a transition is detected, it is coupled through the capacitors and buffered to the p-gate and n-gate nodes. Limiting transistors limit upper and lower node swings.

Abstract: A clock driver for an integrated circuit reduces electro-magnetic interference (EMI) induced in nearby metal traces yet also reduces jitter due to noise at the switching threshold. A weak driver using small n-channel and p-channel transistors initially drives the clock line. Then a pulse generator produces a short pulse to a gate of a large driver transistor. The large driver transistor is pulsed on for a very short period of time. The large driver transistor is turned off by the end of the pulse before the clock line completes its transition. The weak driver then finishes the clock-line transition. Since only the weak driver is on during the start and end of the transition, a slow voltage-slew rate occurs at the beginning and end of the transition. The large driver transistor is on only in the middle of the transition, producing a fast voltage-slew rate in the middle. A triple-slope waveform results.