Patents by Inventor Kwong-Tak A. Chui
Kwong-Tak A. Chui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9344377Abstract: A method to process a packet is described herein. The method comprises receiving a packet including a header and a payload. The header is parsed using a packet processor to determine type and priority of the packet. The header is then processed using a hardware acceleration block based on one or more of incoming bandwidth, priority and type of the packet. The custom hardware acceleration block generates header modification data that is sent to the packet processor. The header is modified using the packet processor, based on the header modification data, to generate a modified header. The modified header is appended to the payload and transmitted.Type: GrantFiled: April 30, 2010Date of Patent: May 17, 2016Assignee: Broadcom CorporationInventors: Fong Pong, Kwong-Tak Chui, Chun Ning, Patrick Lau
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Publication number: 20120030451Abstract: An Parallel and Long Adaptive Instruction Set Architecture (PALADIN) is provided to optimize packet processing. The Instruction Set Architecture (ISA) includes instructions such as aggregate comparison, comparison OR, comparison AND and bitwise instructions. The ISA also includes dedicated packet processing instructions such as hash, predicate, select, checksum and time to live adjust, move header left, post, move header left/right and load/store header/status.Type: ApplicationFiled: August 13, 2010Publication date: February 2, 2012Applicant: Broadcom CorporationInventors: Fong PONG, Kwong-Tak CHUI, Chun NING, Patrick LAU
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Publication number: 20110268119Abstract: A method to process a packet is described herein. The method comprises receiving a packet including a header and a payload. The header is parsed using a packet processor to determine type and priority of the packet. The header is then processed using a hardware acceleration block based on one or more of incoming bandwidth, priority and type of the packet. The custom hardware acceleration block generates header modification data that is sent to the packet processor. The header is modified using the packet processor, based on the header modification data, to generate a modified header. The modified header is appended to the payload and transmitted.Type: ApplicationFiled: April 30, 2010Publication date: November 3, 2011Applicant: Broadcom CorporationInventors: Fong Pong, Kwong-Tak Chui, Chun Ning, Patrick Lau
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Patent number: 7320022Abstract: A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.Type: GrantFiled: July 25, 2002Date of Patent: January 15, 2008Assignee: Broadcom CorporationInventors: Mark D. Hayter, Shailendra S. Desai, Daniel W. Dobberpuhl, Kwong-Tak A. Chui
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Patent number: 7287649Abstract: A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.Type: GrantFiled: May 18, 2001Date of Patent: October 30, 2007Assignee: Broadcom CorporationInventors: Mark D. Hayter, Shailendra S. Desai, Daniel W. Dobberpuhl, Kwong-Tak A. Chui
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Patent number: 7240141Abstract: A method and apparatus for programming instruction issuing rules for instructions residing among various virtual channels, as well as the same virtual channel of an I/O bus interface for a system-on-a-chip processor. In the method and apparatus of the present invention both intra-virtual channel dependencies and inter-virtual channel dependencies are fully programmable, thereby offering significant advantages over prior art I/O interfaces. The method and apparatus of the present invention is broadly comprised of a system for managing data transactions between a first bus and a second bus. A first transaction conversion module is operably connected to the first bus and is operable to receive transactions from the first bus and a first format and to convert those transactions into an internal format.Type: GrantFiled: April 9, 2004Date of Patent: July 3, 2007Assignee: Broadcom CorporationInventors: Chun Hung Ning, Laurent Rene Moll, Kwong-Tak Chui, Shun Wai Go, Piyush Shashikant Jamkhandi
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Patent number: 7003615Abstract: An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write response indicator which is capable of indicating a reception of at least one write response. Each write response indicates that a corresponding write has reached a target device of that write. The write monitor circuit is configured to update the write response indicator in response to receiving an indication of a first write response. A computer accessible medium may comprises instructions which, when executed: (i) initialize the write response indicator; and (ii) issue one or more writes to a target device, wherein the target device is configured to response to each of the writes with a write response to be indicated by the write response indicator.Type: GrantFiled: April 22, 2002Date of Patent: February 21, 2006Assignee: Broadcom CorporationInventors: Kwong-Tak A. Chui, Shun Wai Go, Mark D. Hayter, Chun H. Ning, Amy K. Silveria
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Publication number: 20050228930Abstract: A method and apparatus for programming instruction issuing rules for instructions residing among various virtual channels, as well as the same virtual channel of an I/O bus interface for a system-on-a-chip processor. In the method and apparatus of the present invention both intra-virtual channel dependencies and inter-virtual channel dependencies are fully programmable, thereby offering significant advantages over prior art I/O interfaces. The method and apparatus of the present invention is broadly comprised of a system for managing data transactions between a first bus and a second bus. A first transaction conversion module is operably connected to the first bus and is operable to receive transactions from the first bus and a first format and to convert those transactions into an internal format.Type: ApplicationFiled: April 9, 2004Publication date: October 13, 2005Applicant: Broadcom CorporationInventors: Chun Ning, Laurent Moll, Kwong-Tak Chui, Shun Go, Piyush Jamkhandi
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Patent number: 6851004Abstract: An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected.Type: GrantFiled: July 29, 2003Date of Patent: February 1, 2005Assignee: Broadcom CorporationInventors: James B. Keller, Chun H. Ning, Kwong-Tak A. Chui, Mark D. Hayter
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Publication number: 20040024945Abstract: An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected.Type: ApplicationFiled: July 29, 2003Publication date: February 5, 2004Applicant: Broadcom CorporationInventors: James B. Keller, Chun H. Ning, Kwong-Tak A. Chui, Mark D. Hayter
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Patent number: 6681302Abstract: A system including an agent and a memory controller, in which the agent may initiate transactions targeting a memory to which the memory controller is coupled and the transactions may include a page hint indication. The page hint indication is transmitted during the transaction by the agent, and may be an indication of whether or not the page addressed by the transaction should be kept open or closed. The memory controller may receive the page hint indication. When accessing the storage location(s) in the memory in response to the memory transaction, the memory controller may close the page or keep the page open responsive to the page hint indication.Type: GrantFiled: December 18, 2002Date of Patent: January 20, 2004Assignee: Broadcom CorporationInventors: James Y. Cho, Kwong-Tak A. Chui, Chun H. Ning
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Publication number: 20030200383Abstract: An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write response indicator which is capable of indicating a reception of at least one write response. Each write response indicates that a corresponding write has reached a target device of that write. The write monitor circuit is configured to update the write response indicator in response to receiving an indication of a first write response. A computer accessible medium may comprises instructions which, when executed: (i) initialize the write response indicator; and (ii) issue one or more writes to a target device, wherein the target device is configured to response to each of the writes with a write response to be indicated by the write response indicator.Type: ApplicationFiled: April 22, 2002Publication date: October 23, 2003Inventors: Kwong-Tak A. Chui, Shun Wai Go, Mark D. Hayter, Chun H. Ning, Amy K. Silveria
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Patent number: 6633936Abstract: An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected.Type: GrantFiled: September 26, 2000Date of Patent: October 14, 2003Assignee: Broadcom CorporationInventors: James B. Keller, Chun H. Ning, Kwong-Tak A. Chui, Mark D. Hayter
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Publication number: 20030126383Abstract: A system including an agent and a memory controller, in which the agent may initiate transactions targeting a memory to which the memory controller is coupled and the transactions may include a page hint indication. The page hint indication is transmitted during the transaction by the agent, and may be an indication of whether or not the page addressed by the transaction should be kept open or closed. The memory controller may receive the page hint indication. When accessing the storage location(s) in the memory in response to the memory transaction, the memory controller may close the page or keep the page open responsive to the page hint indication.Type: ApplicationFiled: December 18, 2002Publication date: July 3, 2003Applicant: Broadcom CorporationInventors: James Y. Cho, Kwong-Tak A. Chui, Chun H. Ning
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Patent number: 6526483Abstract: A system including an agent and a memory controller, in which the agent may initiate transactions targeting a memory to which the memory controller is coupled and the transactions may include a page hint indication. The page hint indication is transmitted during the transaction by the agent, and may be an indication of whether or not the page addressed by the transaction should be kept open or closed. The memory controller may receive the page hint indication. When accessing the storage location(s) in the memory in response to the memory transaction, the memory controller may close the page or keep the page open responsive to the page hint indication.Type: GrantFiled: September 20, 2000Date of Patent: February 25, 2003Assignee: Broadcom CorporationInventors: James Y. Cho, Kwong-Tak A. Chui, Chun H. Ning
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Publication number: 20020174255Abstract: A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.Type: ApplicationFiled: July 25, 2002Publication date: November 21, 2002Applicant: Broadcom CorporationInventors: Mark D. Hayter, Shailendra S. Desai, Kwong-Tak A. Chui
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Publication number: 20020174252Abstract: A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.Type: ApplicationFiled: May 18, 2001Publication date: November 21, 2002Applicant: Broadcom CorporaionInventors: Mark D. Hayter, Shailendra S. Desai, Daniel W. Dobberpuhl, Kwong-Tak A. Chui