Abstract: A high-speed serial interface for a programmable logic device includes a plurality of features to handle the various issues that may arise with data rates over 1 Gbps and particularly over 1.25 Gbps. Those features may include dynamic phase alignment to control clock-data skew, data realignment (e.g., bit slip circuitry) to account for channel-to-channel skew, full-duplex serializer and deserializer, out-of-range frequency support for low frequencies, and a soft-CDR mode.

Abstract: A calibration circuit block includes a first resistor network, a second resistor network, and a feedback loop. The first resistor network includes a set of transistors and receives a constant current from a constant current source. The second resistor network receives a tracking current from a tracking current source. The impedance of the second resistor network changes with temperature and process variations on the integrated circuit. The tracking current source compensates for variations in the impedance of the second resistor network that are caused by process and temperature variations to maintain a constant reference voltage at the second resistor network. The feedback loop generates calibration control signals for controlling the conductive states of the transistors in the first resistor network. The feedback loop adjusts the calibration control signals to maintain a constant impedance in the first resistor network.