Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.

Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure including a plurality of peripheral logic circuits disposed on a semiconductor substrate, a horizontal semiconductor layer disposed on the peripheral logic structure, an electrode structure including a plurality of electrodes and insulating layers vertically and alternately stacked on the horizontal semiconductor layer, and a through-interconnection structure penetrating the electrode structure and the horizontal semiconductor layer and including a through-plug connected to the peripheral logic structure. A sidewall of a first insulating layer of the insulating layers is spaced apart from the through-plug by a first distance. A sidewall of a first electrode of the electrodes is spaced apart from the through-plug by a second distance greater than the first distance.

Abstract: Disclosed is a semiconductor memory device comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, a stack structure on the second substrate and comprising a plurality of gate electrodes, a through dielectric pattern penetrating the stack structure and the second substrate, and a vertical supporter on a top surface of the second substrate and vertically extending from the top surface of the second substrate and penetrating the stack structure and the through dielectric pattern.

Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.

Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.

Abstract: Disclosed is a semiconductor memory device comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, a stack structure on the second substrate and comprising a plurality of gate electrodes, a through dielectric pattern penetrating the stack structure and the second substrate, and a vertical supporter on a top surface of the second substrate and vertically extending from the top surface of the second substrate and penetrating the stack structure and the through dielectric pattern.

Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure including a plurality of peripheral logic circuits disposed on a semiconductor substrate, a horizontal semiconductor layer disposed on the peripheral logic structure, an electrode structure including a plurality of electrodes and insulating layers vertically and alternately stacked on the horizontal semiconductor layer, and a through-interconnection structure penetrating the electrode structure and the horizontal semiconductor layer and including a through-plug connected to the peripheral logic structure. A sidewall of a first insulating layer of the insulating layers is spaced apart from the through-plug by a first distance. A sidewall of a first electrode of the electrodes is spaced apart from the through-plug by a second distance greater than the first distance.

Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.