Abstract: A method for IC testing bigdata analysis and option value analysis includes: dividing a wafer into devices under test to undergo an electrical property test, retrieving data detected of the devices under test at different parameters; sorting specific parameters from different parameters according to an intended analysis result; loading a drawing software into a program, defining three-dimensional spatial coordinates, and producing a parameter location map of a three-dimensional cylindrical perspective graphic in three-dimensional spatial coordinates according to coordinate points X, Y, Z.

Abstract: A wafer map identification system for wafer test data includes a capturing unit configured to collect the test data of each wafer chip from the wafer testing device; an execution interface for receiving the test data from the capturing unit and generating a wafer map, the wafer map defining a plurality of color blocks with respect to locations of the test chips, each of the color blocks having a color defined by a grade of the respective test chip. Moreover, each color block reveals the associated test data as being pointed.

Abstract: A wafer test data analysis method. A test wafer is divided into a plurality of test chips. Each of the test chips is tested for electrical property and captured data under various parameters. A specific parameter is sorted from the parameters according to a requirement of an analysis result. Defining a three-dimensional space coordinate, the three-dimensional space coordinate has a plurality of coordinate points (X, Y, Z) to create a three-dimensional parameter location map and a three-dimensional bin-bar map.