Abstract: A cooling device includes a first surface portion thermally connected to one or more heating elements, a second surface portion opposed to the first surface portion, a flow path between the first and second surface portions and through which the cooling fluid flows, and a side wall connecting the first and second surface portions and extending along the direction in which the cooling fluid flows. A height of the side wall is reduced from the second surface portion side toward the first surface portion side at an outlet of the flow path. At least a portion of the second surface portion is missing in a portion of the side wall of which the height is reduced. A portion where the side wall is in contact with the first surface portion is superimposed on at least an entirety of the heating element closest to the outlet of the flow path.

Abstract: An optical unit includes a movable body including an optical module, a fixed body, a support mechanism, a flexible printed circuit board, and a fixing part. The fixing part is superposed on a bent part formed by bending the flexible printed circuit board. At least a part of the fixing part is fixed to the bent part of the flexible printed circuit board.

Abstract: A heat dissipator includes a metal plate including a first surface through which fluid flows, first protrusions on the first surface, a recess in the first surface and between the first protrusions, and a second surface in contact with a heating element on an opposite side of the first surface.

Abstract: A multi-chip package structure is provided with a first chip, a substrate adjacent to the first chip, a plurality of contacts connecting the first chip and the substrate, a second chip disposed between the first chip and the substrate and connecting to the first chip, and a underfill film, wherein the underfill film covers the contact to isolate the contact from the second chip, wherein an empty space is defined by the second chip and the substrate so that the second chip does not contact the substrate.

Abstract: A light-emitting semiconductor packaging structure without wire bonding, including a heat conduction board, a light-emitting semiconductor chip bonded on the heat conduction board and a lead frame positioned around the chip. The lead frame has at least one connection section extending to upper side of the chip to connect with a conductive protruding block adhered to an active surface of the chip. The conductive protruding block is bonded with the chip and the connection section of the lead frame by larger area so that the heat conduction area is increased to enhance heat dissipation effect for the chip. It is unnecessary to save upward and outward extension room for wire bonding so that the volume and thickness of the packaging structure are minified. The chip is received in a cavity of the lead frame to form a lightweight and miniaturized heat dissipation packaging structure.

Abstract: A flat-plate loop heat conduction device and a manufacturing method thereof. The flat-plate loop heat conduction device includes an upper flat plate and a lower flat plate overlapping and mating with each other. Complementary partial evaporation sections, partial vapor transfer pipes, partial condensing sections and partial condensing transfer pipes are disposed on the upper and lower flat plates. After the upper and lower flat plates are mated with each other, a complete evaporation section, a complete condensing section, a complete vapor transfer pipe and a complete condensing transfer pipe are formed in communication with each other to achieve a heat conduction loop structure for a working fluid to circulate therein. The flat-plate loop heat conduction device is easier to manufacture. Moreover, the flat-plate loop heat conduction device has reinforced structure and is not subject to damage.

Abstract: A chip package including a chip, a package substrate, and a plurality of bumps is provided. The chip has a plurality of chip pads disposed on a surface of the chip. The package substrate has a plurality of first substrate pads, a plurality of second substrate pads, and a surface bonding layer. The first substrate pads and second substrate pads are disposed on a surface of the package substrate. The surface bonding layer is disposed on the first substrate pads and second substrate pads, and covers a part of each second substrate pad. The bumps are respectively disposed between the chip pads and the surface bonding layer. The chip is electrically connected to the package substrate through the bumps. Each first substrate pad is electrically connected to one of the bumps, and each second substrate pad is electrically connected to at least two of the bumps.

Abstract: An electronic apparatus including a main board, an input/output (I/O) board, and a flexible printed circuit (FPC) is provided. The main board includes a first carrier, a central processing unit (CPU), a north bridge unit, a south bridge unit, a basic input/output system (BIOS), a memory module, a clock generator, a graphic unit, and at least one power management. The CPU, the north bridge unit, the south bridge unit, the BIOS, the memory module, the clock generator, the graphic unit, and the power management are disposed on the first carrier. The I/O board includes a second carrier an I/O module and an I/O connector. The I/O module and the I/O connector are disposed on the second carrier. The FPC connects the first carrier and the second carrier.

Abstract: A manufacturing process of a chip package structure is provided. The manufacturing method uses fine pitch circuit processes, such as a TFT-LCD process or an IC process, to increase layout density and shorten electrical transmission pathways so that a higher electrical performance level is attained. First, a multi-layered interconnection structure with high-density bonding pads and fine pitch circuit is formed over a hard support base plate having a large area and high degree of planarity. A die is attached to a top surface of the multi-layered interconnection structure. A plurality of opening is formed on a bottom surface of the support base plate. Contacts are positioned into the openings in the support base plate such that the contacts are electrically connected to an inner circuit within the multi-layered interconnection structure.

Abstract: A multi-chip package structure is provided with a first chip, a substrate adjacent to the first chip, a plurality of contacts connecting the first chip and the substrate, a second chip disposed between the first chip and the substrate and connecting to the first chip, and a underfill film, wherein the underfill film covers the contact to isolate the contact from the second chip, wherein an empty space is defined by the second chip and the substrate so that the second chip does not contact the substrate.

Abstract: The present invention provides a chip and its manufacturing methods and applications. Regarding the chip, there are several solder bumps on the backside of the chip. The difference of the invented chip from the convention chips is that the solder bumps are embedded in an insulting layer and a thermal-plastic material layer of the invented chip backside and separated by a conductive layer from the insulting layer and thermal-plastic material layer. Additionally, there are some end members in the insulting layer, and the end member corresponds to one solder bump. Through the present invention, chips with different functions can be integrated together, so that the needs for having portable communication devices lighter and smaller would be met.

Abstract: A multi-conducting through hole structure is provided. The multi-conducting through hole structure has a substrate, at least two signal lines and at least a reference line. The substrate has a through hole passing therethrough. The signal lines are disposed on a portion of an inner surface of the through hole and extended through the through hole. The reference line is disposed on a portion of the inner surface of the through hole and extended through the through hole, wherein the reference line is disposed between the lines for signal. Because the signal lines are separated by the reference line, the electromagnetic coupling generated by signals can be reduced to lower the cross-talk interference between signals passing through the through hole, so as to promote the signal-transmission quality.

Abstract: A chip package includes a chip, a carrier, and at least a bump connecting structure for connecting the chip to the carrier. The bump connecting structure includes a first metal bump disposed on a chip pad of the chip and has a first height relative to a passivation layer of the chip, a second metal bump disposed on a carrier pad of the carrier and has a second height relative to a solder mask layer of the carrier, and a middle metal part disposed between the first and the second metal bumps. The sum of the minimum distance between the first and the second metal bumps, the first height of the first metal bump, and the second height of the second metal bump is less than 60 micrometers. The melting point of the middle metal part is lower than that of the first and the second metal bumps.

Abstract: The present invention provides a chip and its manufacturing methods and applications. Regarding the chip, there are several solder bumps on the backside of the chip. The difference of the invented chip from the convention chips is that the solder bumps are embedded in an insulting layer and a thermal-plastic material layer of the invented chip backside and separated by a conductive layer from the insulting layer and thermal-plastic material layer. Additionally, there are some end members in the insulting layer, and the end member corresponds to one solder bump. Through the present invention, chips with different functions can be integrated together, so that the needs for having portable communication devices lighter and smaller would be met.

Abstract: An electronic apparatus including a substrate, a baseband component and an electronic assembly is disclosed. The substrate has a first surface and a second surface opposite to the first surface. The baseband component is disposed on the first surface and electrically connected to the substrate. The electronic assembly includes an integrated passive device and a radio frequency component. The integrated passive device is disposed on the second surface and electrically connected to the substrate. The radio frequency component is disposed on the integrated passive device and electrically connected to the integrated passive device.

Abstract: A build-up layer packaging comprising a first ceramic substrate, a second ceramic substrate, and a circuit layer is provided. The first ceramic substrate has a through hole to dispose a die therein. The second ceramic substrate, attached to a common lower surface of the ceramic substrate and the die, further has a plurality of openings to expose the pads of the die. The openings are filled with plugs electrically connecting to the pads. The circuit layer is formed under the second ceramic substrate to transmit signals generated by the die outward.

Abstract: A chip package including a chip, a package substrate, and a plurality of bumps is provided. The chip has a plurality of chip pads disposed on a surface of the chip. The package substrate has a plurality of first substrate pads, a plurality of second substrate pads, and a surface bonding layer. The first substrate pads and second substrate pads are disposed on a surface of the package substrate. The surface bonding layer is disposed on the first substrate pads and second substrate pads, and covers a part of each second substrate pad. The bumps are respectively disposed between the chip pads and the surface bonding layer. The chip is electrically connected to the package substrate through the bumps. Each first substrate pad is electrically connected to one of the bumps, and each second substrate pad is electrically connected to at least two of the bumps.

Abstract: A chip carrier comprising a laminated layer and an oxidation protection layer is provided. The oxidation protection layer is a non-electrolytic metallic coating or an organic oxidation protection film on the surface of bonding finger pads or other contacts formed by deploying a simple, fast film-coating technique. Therefore, there is no need to plate a Ni/Au layer on the bonding pads or contacts using expensive electroplating equipment for preventing oxidation and there is no need to fabricate plating lines on the chip carrier or reserve space for laying out the plating lines. Thus, the cost for fabricating the chip carrier is reduced, the effective area of the chip carrier is increased and the electrical performance of the chip carrier is improved.

Abstract: A semiconductor package including a die, a substrate and bumps is provided. The die has die pads arranged on an active surface thereof and a first passivation layer. The first passivation layer is disposed on the active surface and has first openings for exposing the die pads, respectively. The substrate has a substrate surface, substrate pads and a second passivation layer. The substrate pads are arranged on the substrate surface. The second passivation layer is arranged on the substrate surface and has a second opening for exposing the substrate pads and a portion of the substrate surface. The bumps are arranged on the die pads, respectively. Each bump is connected to one of the substrate pads through a compression bonding process, and the die is electrically connected to the substrate through the bumps. A distance between the first passivation layer and the substrate pads is smaller than 50 ?m.

Abstract: A process for mounting conductive blocks on a surface of a substrate is disclosed wherein the substrate may be an IC chip, carrier, or a PCB. An adhesive layer is formed on each of the pads of the substrate. Thereafter, a plurality of conductive blocks are scattered on the surface of the substrate. The conductive blocks are vibrated such that only one of the conductive blocks is attached to the adhesive layer of each pad. After removing the un-attached conductive blocks from the surface of the substrate, and the remaining conductive blocks become the conductive blocks for electrical connection.