Patents by Inventor Ky Yang

Ky Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6413817
    Abstract: A method of forming a self-aligned stacked capacitor on a substrate having a first insulation layer thereon. A bit line contact and a first section node contact are formed in the first insulation layer, and then a bit line structure is formed over the first insulation layer. The bit line structure includes a bit line, a cap layer and spacers. The bit line and the bit line contact are electrically connected. The cap layer is formed above the bit line while the spacers are formed on the sidewalls of the bit line and the cap layer. A second insulation layer, an etching stop layer and a third insulation layer are sequentially formed over the substrate. An opening is formed in the third insulation layer, the etching stop layer and the second insulation layer to expose a portion of the bit line structure and the first section node contact. A conformal first conductive layer is formed over the interior surface of the opening.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: July 2, 2002
    Assignee: United Microelectronic Corp.
    Inventors: Wunn-Shien Liao, Ching-Ming Lee, Ky Yang
  • Publication number: 20020022321
    Abstract: A method of forming a self-aligned stacked capacitor on a substrate having a first insulation layer thereon. A bit line contact and a first section node contact are formed in the first insulation layer, and then a bit line structure is formed over the first insulation layer. The bit line structure includes a bit line, a cap layer and spacers. The bit line and the bit line contact are electrically connected. The cap layer is formed above the bit line while the spacers are formed on the sidewalls of the bit line and the cap layer. A second insulation layer, an etching stop layer and a third insulation layer are sequentially formed over the substrate. An opening is formed in the third insulation layer, the etching stop layer and the second insulation layer to expose a portion of the bit line structure and the first section node contact. A conformal first conductive layer is formed over the interior surface of the opening.
    Type: Application
    Filed: October 5, 2001
    Publication date: February 21, 2002
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wunn-Shien Liao, Ching-Ming Lee, Ky Yang