Patents by Inventor KyawSwa Maung

KyawSwa Maung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7710205
    Abstract: A method and apparatus for detecting capacitive devices are disclosed. A circuit including two circuit paths is connected to an oscillator voltage source. Connecting a test capacitive device to a path of the circuit modifies the electric potential waveform at a point along the path. Passing the first circuit path through a reference comparator and the second circuit path through a phase-shifting comparator produces two output signals that are phase-shifted with respect to each other when the test capacitive device is functional. Analysis of the output signals allows detection or measurement of the test capacitive device.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: May 4, 2010
    Assignee: Seagate Technology LLC
    Inventors: KyawSwa Maung, Manoj Dey
  • Publication number: 20070120608
    Abstract: A method and apparatus for detecting capacitive devices are disclosed. A circuit including two circuit paths is connected to an oscillator voltage source. Connecting a test capacitive device to a path of the circuit modifies the electric potential waveform at a point along the path. Passing the first circuit path through a reference comparator and the second circuit path through a phase-shifting comparator produces two output signals that are phase-shifted with respect to each other when the test capacitive device is functional. Analysis of the output signals allows detection or measurement of the test capacitive device.
    Type: Application
    Filed: November 28, 2005
    Publication date: May 31, 2007
    Inventors: KyawSwa Maung, Manoj Dey
  • Patent number: 6807507
    Abstract: An apparatus and associated method for testing an integrated circuit for electrical over stress includes a spike source configured to couple to an input of the integrated circuit, and responsively provide a signal spike to the input, and a current sensor configured to couple to a power supply. The power supply is coupled to the integrated circuit to provide power to the integrated circuit. The current sensor provides a sensor output related to the current supply to the integrated circuit from the power supply. The apparatus also includes test circuitry coupled to the sensor output configured to provide a failure output in response to a characteristic increase in power supply current sensed by the current sensor in response to an applied signal spike.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: October 19, 2004
    Inventors: Vasudevan Seshadhri Kumar, Manoj Kumar Dey, Pooranampillai Samuel Pooranakaran, KyawSwa Maung
  • Publication number: 20030101016
    Abstract: An apparatus and associated method for testing an integrated circuit for electrical over stress includes a spike source configured to couple to an input of the integrated circuit, and responsively provide a signal spike to the input, and a current sensor configured to couple to a power supply. The power supply is coupled to the integrated circuit to provide power to the integrated circuit. The current sensor provides a sensor output related to the current supply to the integrated circuit from the power supply. The apparatus also includes test circuitry coupled to the sensor output configured to provide a failure output in response to a characteristic increase in power supply current sensed by the current sensor in response to an applied signal spike.
    Type: Application
    Filed: June 27, 2002
    Publication date: May 29, 2003
    Inventors: Vasudevan Seshadhri Kumar, Manoj Kumar Dey, Pooranampillai Samuel Pooranakaran, KyawSwa Maung