Patents by Inventor Kye-Soon Park

Kye-Soon Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11976975
    Abstract: Provided is an optical system which may acquire a hyperspectral image by acquiring a spectral image of an object to be measured, which includes, to collect spectral data and train the neural network, an image forming part forming an image from an object to be measured and transmitting collimated light, a slit moving to scan the incident image and passing and outputting a part of the formed image, and a first optical part obtaining spectral data by splitting light of the image received through the slit by wavelength. Also, the system includes, to decompose overlapped spectral data and to infer hyperspectral image data through the trained neural network, an image forming part forming an image from an object to be measured and transmitting collimated light, and a first optical part obtaining spectral data by splitting light of the received image by wavelength.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: May 7, 2024
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Keo Sik Kim, Kye Eun Kim, Jeong Eun Kim, Hyun Seo Kang, Hyun Jin Kim, Gi Hyeon Min, Si Woong Park, Hyoung Jun Park, Chan Il Yeo, Young Soon Heo
  • Patent number: 7332761
    Abstract: The present invention relates to a method for fabricating a capacitor of a semiconductor device.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: February 19, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Nam-Jae Lee, Kye-Soon Park
  • Patent number: 7208406
    Abstract: Disclosed is a method for forming a gate in a semiconductor device. The method includes the steps of: sequentially forming a gate insulation layer and an inter-layer insulation layer on a substrate; patterning the inter-layer insulation layer into a predetermined configuration, thereby forming a patterned inter-layer insulation layer; forming a nitride layer on the patterned inter-layer insulation layer; simultaneously etching the nitride layer and the substrate, thereby obtaining a spacer on sidewalls of the patterned inter-layer insulation layer and a trench having a predetermined depth in the substrate; forming a conductive layer on the trench; and planarizing the conductive layer, thereby forming the gate.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 24, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kye-Soon Park
  • Patent number: 7129131
    Abstract: A method for fabricating a capacitor of a semiconductor device. The semiconductor device includes: a bit line structure formed on a substrate and including stacked layers of a bit line, a hard mask and a spacer. The spacer is formed along a profile containing the bit line and the hard mask. A first inter-layer insulation layer is deposited on an entire surface of the bit line structure. A storage node contact plug is formed on the substrate by passing through the inter-layer insulation layer and having a partially etched portion. A second inter-layer insulation layer is formed on a partial portion of the first inter-layer insulation layer and the storage node contact plug.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: October 31, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Nam-Jae Lee, Kye-Soon Park
  • Publication number: 20060124984
    Abstract: The present invention relates to a method for fabricating a capacitor of a semiconductor device.
    Type: Application
    Filed: February 9, 2006
    Publication date: June 15, 2006
    Inventors: Nam-Jae Lee, Kye-Soon Park
  • Publication number: 20050142809
    Abstract: Disclosed is a method for forming a gate in a semiconductor device. The method includes the steps of: sequentially forming a gate insulation layer and an inter- layer insulation layer on a substrate; patterning the inter- layer insulation layer into a predetermined configuration, thereby forming a patterned inter-layer insulation layer; forming a nitride layer on the patterned inter-layer insulation layer; simultaneously etching the nitride layer and the substrate, thereby obtaining a spacer on sidewalls of the patterned inter-layer insulation layer and a trench having a predetermined depth in the substrate; forming a conductive layer on the trench; and planarizing the conductive layer, thereby forming the gate.
    Type: Application
    Filed: June 28, 2004
    Publication date: June 30, 2005
    Inventor: Kye-Soon Park
  • Publication number: 20040262662
    Abstract: A method for fabricating a capacitor of a semiconductor device. The semiconductor device includes: a bit line structure formed on a substrate and including stacked layers of a bit line, a hard mask and a spacer. The spacer is formed along a profile containing the bit line and the hard mask. A first inter-layer insulation layer is deposited on an entire surface of the bit line structure. A storage node contact plug is formed on the substrate by passing through the inter-layer insulation layer and having a partially etched portion. A second inter-layer insulation layer is formed on a partial portion of the first inter-layer insulation layer and the storage node contact plug.
    Type: Application
    Filed: December 18, 2003
    Publication date: December 30, 2004
    Inventors: Nam-Jae Lee, Kye-Soon Park