Abstract: A liquid crystal display device includes upper and lower pixels; gate lines in electrical connection with the adjacent pixels and extending in a row direction, and data lines which cross the gate lines; and a reference voltage line including a vertical portion which passes through the adjacent pixels, and horizontal portions which alternately extend from the vertical portion. Each of the adjacent pixels includes first and second thin film transistors (TFTs) each in electrical connection with a gate line and a data line which correspond to a respective pixel; and a pixel electrode including a first subpixel electrode in connection with an output terminal of the first TFT, and a second subpixel electrode in connection with an output terminal of the second TFT. The horizontal portions of the reference voltage line are in electrical connection with the second subpixel electrodes of the adjacent pixels.

Abstract: A display substrate is disclosed. In one aspect, the substrate includes a first substrate which includes a first display region, a first peripheral region and a first seal-line region and a second substrate facing the first substrate and including a second display region, a second peripheral region and a second seal-line region. The substrate also includes a sealing member formed on the first seal-line region and the second seal-line region to affix the first and second substrates and a color filter formed in the first display region. The substrate further includes a first dam formed using the same material as the color filter, formed in the first peripheral region, adjacent to the first seal-line region in the first peripheral region and a second dam formed using the same material as the color filter and formed adjacent to the first display region in the first peripheral region.

Abstract: A liquid crystal display device includes upper and lower pixels; gate lines in electrical connection with the adjacent pixels and extending in a row direction, and data lines which cross the gate lines; and a reference voltage line including a vertical portion which passes through the adjacent pixels, and horizontal portions which alternately extend from the vertical portion. Each of the adjacent pixels includes first and second thin film transistors (TFTs) each in electrical connection with a gate line and a data line which correspond to a respective pixel; and a pixel electrode including a first subpixel electrode in connection with an output terminal of the first TFT, and a second subpixel electrode in connection with an output terminal of the second TFT. The horizontal portions of the reference voltage line are in electrical connection with the second subpixel electrodes of the adjacent pixels.

Abstract: A liquid crystal display device includes upper and lower pixels; gate lines in electrical connection with the adjacent pixels and extending in a row direction, and data lines which cross the gate lines; and a reference voltage line including a vertical portion which passes through the adjacent pixels, and horizontal portions which alternately extend from the vertical portion. Each of the adjacent pixels includes first and second thin film transistors (TFTs) each in electrical connection with a gate line and a data line which correspond to a respective pixel; and a pixel electrode including a first subpixel electrode in connection with an output terminal of the first TFT, and a second subpixel electrode in connection with an output terminal of the second TFT. The horizontal portions of the reference voltage line are in electrical connection with the second subpixel electrodes of the adjacent pixels.

Abstract: An exemplary embodiment of a display panel according to the present invention includes; a substrate, a display area including a gate line disposed on the substrate, and a gate driver connected to one end of the gate line, the gate driver including a plurality of stages disposed in a first direction, and integrated on the substrate, wherein the gate driver includes; a plurality of clock signal lines extending in the first direction and a voltage signal line extending in the first direction, and the voltage signal line disposed between the plurality of clock signal lines and the plurality of stages.