Abstract: A memory device includes: memory cells of first and second planes; and a control circuit suitable for performing multiple read operations on the memory cells in response to a read command. The multiple read operations may include a first read operation which is performed on the memory cells of the first plane in a first read period and a second read operation which is performed on the memory cells of the second plane in a second read period.

Abstract: A memory device may include: a memory cell array including a plurality of memory cells; and a control circuit suitable for programming the memory cell array. The control circuit may program the memory cell array according to a predetermined coding method, such that read voltage levels for multi-sensing are minimized and the numbers of read operations for logical pages are distributed. Therefore, the memory device can improve the cell distribution for the plurality of memory cells and the performance of read timing.

Abstract: A memory device includes: memory cells of first and second planes; and a control circuit suitable for performing multiple read operations on the memory cells in response to a read command. The multiple read operations may include a first read operation which is performed on the memory cells of the first plane in a first read period and a second read operation which is performed on the memory cells of the second plane in a second read period.

Abstract: A memory device may include: a memory cell array including a plurality of memory cells; and a control circuit suitable for programming the memory cell array. The control circuit may program the memory cell array according to a predetermined coding method, such that read voltage levels for multi-sensing are minimized and the numbers of read operations for logical pages are distributed. Therefore, the memory device can improve the cell distribution for the plurality of memory cells and the performance of read timing.

Abstract: A word line voltage regulation circuit includes a first comparator for comparing a first reference voltage and the potential of an output node; a first switching element for supplying the supply voltage to the output node depending on the output signal of the first comparator; a second comparator for comparing a second reference voltage and the potential of the output node; a second switching element for regulating the potential of the output node depending on the output signal of the second comparator; a third switching element for transmitting the potential of the output node to a decoder circuit depending on a first control signal; and a fourth switching element for supplying the supply voltage to the decoder circuit depending on a second control signal.

Abstract: (The present invention discloses) a method of pre-programming a flash memory cell. According to the present invention, it makes it possible to execute a continuous programming by performing a pre-programming step of internal algorithms with a bulk program verification step not with a byte or word pre-programming step when an erasure operation of a flash memory cell using a stack gate cell is performed.

Abstract: This invention discloses a method of erasing a flash memory, in which the method comprises: (A) erasing all cells of a selected sector; (B) verifying in cells whether the cells are erased; (C) saving an address corresponding to a non-erased cell and re-erasing the cells when the non-erased cell is detected by the step (B); (D) verifying in cells, from the saved address to the final address whether the cells are erased; and (E) executing a slight-program for recovering over-erased cells so that the cells of the sector are normally erased.